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RE: [N8VEM-S100:233] 4M Boards (was: S-100 dual IDE board)

I don't actually remember that one Mike, do you Andrew?  It's been a while,
but besides using 74Fxx the only way I could see cutting down the access
time on that board would be to use a PAL. Remember the board is setup to
accommodate the S-100 bus  which has two separate buses, one  for 8 bits and
one bidirectional bus for 16 bits.

I am already thinking how I will be doing 80486's, Pentiums etc. in the
future. I think the best way will be to have the RAM on the same CPU board
with surface mount RAM chips etc.  Somebody here told me there are outfits
that will place the chips for you. Need to look into that.  Just use the
S-100 bus for IO etc.

Anyway a bit into the future.

-----Original Message-----
From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On
Behalf Of mike
Sent: Sunday, May 29, 2011 5:00 PM
To: n8vem...@googlegroups.com
Subject: Re: [N8VEM-S100:233] 4M Boards (was: S-100 dual IDE board)

Hash: SHA1


On those 4M boards. Will those include the any timing modifications in
support of the 68K CPU? I recall reading on one of the sites that there was
potentially going to be a modification in reduce the amount of propagation
delay in the read timing in order that an 'F IC might not be required in
place of an 'LS. I'm sorry I've lost the link to that article, but does any
of this ring a bell? And will the the next 4M boards include any such

Meanwhile if I stumble on that page again, I'll bookmark it.

Kind Regards,

Mike Sharkey

On 11-05-29 11:57 AM, Andrew Lynch wrote:
>  Sorry, I am out of the S-100 4MB SRAM boards although I can add you 
> to the waiting list for the next batch if you would like.
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