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RE: [N8VEM-S100:995] Clock generator for S-100 80386 Board.
Very interesting Mike, looks like a fair amount or real estate would be required but I had not thought of that approach. Will read up on it.
BTW, it looks like I can get the VT8225N's from UTSource. (only $4 each). Will do so just in case I need it, however I beginning to conclude that if I just slam multiple wait states (0-16), on the 386 for any cycle that is an I/O cycle, an INTA or RAM <1MG (say) I should be able to access the S-100 bus in a manner that looks like say an 8MHz system.
If I understand the 386 signals correctly all the Address, BHE0-3, M/IO, R/W, D/C signals are stretched (apparently with no upper limit) by raising the READY input. This would make it possible to have low frequency S-100 address, status and control signals. The only two 386 lines that are not affected are ADS* (from the 386) and CLK2 going to the 386, but also to the S-100 bus as clock (pin 24). I hoping I can get away with dividing this signal to the bus (only), down since on the bus it is actually seldom used and if so only for clocking 7474's etc. However I'm using ADS* to replicate pSYNC and pSTVAL. This may be more problematic. Will try using the "stretched" clock to stretch them.
What all this has going for it Mike is the whole circuit is quite simple and indeed is quite similar to the current 80286 working prototype board. Will send schematic when Andrew has a chance to combine and draw up all my diagrams, but I would like to know what you think of the above approach before I go further.
John Monahan Ph.D
From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of mike
Sent: Friday, July 20, 2012 9:11 AM
Subject: Re: [N8VEM-S100:995] Clock generator for S-100 80386 Board.
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If you where also to use an i82385 (or so) cache controller with a small amount of on-board fast static RAM, then I think you could maintain pretty decent performance by avoiding a lot of S-100 bus transactions.
On 07/20/2012 05:17 AM, Pontus Oldberg wrote:
> I would recommend you build a 386 local bus <-> S-100 bridge. This
> bridge would generate all S-100 signals with correct timing and
> relationship while holding the 386 in wait state. This way you can run
> the S-100 bus at max speed while slowing the processor down only while
> accessing the bus. I guess a CPLD or a few PLD's and buffers (which
> you already need) would do the trick.
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