Thanks Douglas, the hard part will be phase 3, getting a DRAM controller with 1-4GB RAM!
Thanks John for the update. This looks like a very interesting board.
I for one will be watching for the board and daughterboard to reach the point where I can think about Concurrent.
On Oct 16, 2012, at 3:42 PM, John Monahan <mon...@vitasoft.org> wrote:
In case you missed it on one of the web postings I would like to mention that Andrew Lynch and I have just completed a prototype of a new 80386 Master/Slave CPU S-100 bus board. This exciting board is capable of reaching up to12MHz in an S-100 system with an active terminated bus.
This is an ongoing project. It utilizes the 16 bit mode of the 80386 to address the 16MG of RAM the S-100 bus is capable of addressing. A second daughter board system with an overhead ribbon cable connector is planned to for daughter board(s) to enlarge the RAM space up to the 4GB the CPU is capable of addressing (using high density static and DRAM chips).
If you would like to read about this board please look here:-
It is too early to accept “orders” for this board, but if you would like to be kept in the loop as this board evolves keep an eye on the above page.