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Re: [N8VEM-S100:1447] New/Old Project (Altair restoration)
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- Subject: Re: [N8VEM-S100:1447] New/Old Project (Altair restoration)
- From: Rob Doyle <radi...@gmail.com>
- Date: Sat, 23 Feb 2013 22:04:51 -0700
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The output from the 8080 is a healthy 4.9V where it goes into the
74LS367, but on the output side it is only 3.4V. This low voltage
value for a high logic state seems like a potential problem to me. Am
The TTL output voltages are described by the VOH (Output High) and the
VOL (Output Low) specifications in the data sheet.
It is normal for TTL the minimum VOH to be 2.7V and a maximium VOL to be
0.5V. IOW, a TTL output is guaranteed to be above 2.7V when high and
below 0.5V when low.
Conversely the TTL input voltages are described by the VIH (Input High)
and the VIL (Input Low) specifications in the data sheet.
A typical minimum VIH is 2.0V and a maximum VIL is 0.8V. Therefore a
worst-case output can drive a worst-case input with good margin
including some amount of loading.
There isn't anything wrong with the voltages that you've measured.
Note: the above applies to TTL voltages. If I recall correctly, the
i8080 is an NMOS device so none of the above description applies to the
inputs or outputs of the i8080. NMOS has a completely different output
structure (depletion mode FET to VDD) which is why you're seeing higher
output voltages. That's not to say that the TTL and NMOS circuitry are
incompatible with each other.