alt_sld_fab |

2018.10.11.20:46:28 | Datasheet

Overview

Memory Map

## alt_sld_fab

alt_sld_fab v18.0

## Parameters
DESIGN_HASH | 7e435162c3170612d198
NODE_COUNT | 1
MAX_WIDTH | 31
SETTINGS | {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 0 ir_width 8 psig 9b67919e}
CLOCKS | {id {} }
AGENTS |
EP_INFOS | {hpath {ROM1:inst78|altsyncram:altsyncram_component|altsyncram_45c1:auto_generated|sld_mod_ram_rom:mgl_prim2} }
MIRROR | 0
TOP_HUB | 1
COMPOSED_SETTINGS | {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 0 ir_width 8 bridge_agent 0 prefer_host {} }
DEVICE_FAMILY | CYCLONEIVE
AUTO_DEVICE | Unknown
AUTO_DEVICE_SPEEDGRADE | Unknown
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_presplit

altera_super_splitter v18.0

## Parameters
MAX_WIDTH | 31
SEND_WIDTHS | 10
RECEIVE_WIDTHS | 31
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_splitter

altera_sld_splitter v18.0

alt_sld_fab_presplit | pass | alt_sld_fab_splitter
nodes
alt_sld_fab_sldfabric | clock_0
clock_0
node_0
node_0

## Parameters
FRAGMENTS | {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_0} } moduleassign {debug.virtualInterface.link_0 {debug.endpointLink {fabric sld index 1} } } } }
EXAMPLE |
ADD_INTERFACE_ASGN | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_jtagpins

altera_jtag_pins_bridge v18.0

## Parameters
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_sldfabric

altera_sld_jtag_hub v18.0

alt_sld_fab_jtagpins | clock | alt_sld_fab_sldfabric
clock
node
node
|  | clock_0 | alt_sld_fab_splitter
|  | clock_0
|  | node_0
|  | node_0
|  | ident | alt_sld_fab_ident
|  | ident_0

## Parameters
DEVICE_FAMILY | CYCLONEIVE
SETTINGS | {mfr_code 110 type_code 3 version 2 instance 0 ir_width 8 bridge_agent 0 prefer_host {} }
COUNT | 1
N_SEL_BITS | 1
N_NODE_IR_BITS | 8
NODE_INFO | 00010000000110000110111000000000
COMPILATION_MODE | 0
BROADCAST_FEATURE | 0
FORCE_IR_CAPTURE_FEATURE | 1
FORCE_PRE_1_4_FEATURE | 0
NEGEDGE_TDO_LATCH | 1
ENABLE_SOFT_CORE_CONTROLLER | 0
TOP_HUB | 1
CONN_INDEX | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_sld_fab_ident

altera_connection_identification_hub v18.0

alt_sld_fab_sldfabric | ident | alt_sld_fab_ident
ident_0

## Parameters
DESIGN_HASH | 7e435162c3170612d198
COUNT | 1
SETTINGS | {width 4 latency 0}
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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