
State Machine - |FPGA_Board_UART|uart:inst13|tx_state
Name tx_state.TX_IDLE tx_state.TX_DELAY_RESTART tx_state.TX_SENDING 
tx_state.TX_IDLE 0 0 0 
tx_state.TX_SENDING 1 0 1 
tx_state.TX_DELAY_RESTART 1 1 0 

State Machine - |FPGA_Board_UART|uart:inst13|recv_state
Name recv_state.RX_RECEIVED recv_state.RX_ERROR recv_state.RX_DELAY_RESTART recv_state.RX_CHECK_STOP recv_state.RX_READ_BITS recv_state.RX_CHECK_START recv_state.RX_IDLE 
recv_state.RX_IDLE 0 0 0 0 0 0 0 
recv_state.RX_CHECK_START 0 0 0 0 0 1 1 
recv_state.RX_READ_BITS 0 0 0 0 1 0 1 
recv_state.RX_CHECK_STOP 0 0 0 1 0 0 1 
recv_state.RX_DELAY_RESTART 0 0 1 0 0 0 1 
recv_state.RX_ERROR 0 1 0 0 0 0 1 
recv_state.RX_RECEIVED 1 0 0 0 0 0 1 
