S100 Computers - SCSI Board

The NCR 5380 SCSI bus controller is a classic single-chip interface designed to connect a microprocessor system (such as an 8-bit or 16-bit CPU) to a SCSI peripheral bus. Introduced in the early 1980s, it implements the core functions required by the SCSI-1 standard, including bus arbitration, selection/reselection, and control of data transfer phases. Rather than being a complete “smart” controller, the 5380 is often described as a low-level or “dumb” SCSI controller, meaning that much of the protocol handling is managed in software by the host CPU. This made it flexible and relatively inexpensive, which is why it appeared in many early workstations, expansion cards, and embedded systems.

Technically, the 5380 provides an 8-bit parallel data path and a set of registers that allow the host system to directly manipulate SCSI control signals such as REQ, ACK, BSY, SEL, and ATN. It supports both programmed I/O and limited DMA-style transfers (often with the help of an external DMA controller like the Intel 8237). Because it exposes the SCSI bus phases quite directly, software must actively manage handshaking and timing during reads and writes. This results in higher CPU overhead compared to later SCSI chips, but also gives developers fine-grained control—something that made the 5380 popular in custom and experimental designs.

Historically, the 5380 became one of the most widely used early SCSI interface chips and helped establish SCSI as a practical standard for connecting disks, tape drives, and other peripherals. It was used in a variety of systems ranging from early UNIX workstations to add-on boards for personal computers. Later generations of controllers—such as the NCR 53C90 and more advanced SCSI ASICs—integrated more intelligence and offloaded protocol handling from the CPU. Even so, the 5380 remains well known among retro-computing and embedded-systems enthusiasts for its simplicity, transparency, and foundational role in the evolution of SCSI technology.

The NCR 5380 SCSI bus controller supports several different programming and data-transfer modes, ranging from very simple CPU-controlled transfers to higher-speed DMA-assisted operation. The chip itself is relatively low level, so the host processor still manages much of the SCSI protocol in software, but the various modes determine how data bytes move between the SCSI bus and system memory.

The simplest mode is usually called Programmed I/O (PIO) or polled mode. In this mode, the CPU continuously watches the 5380 status bits to determine when the target device is ready for another byte. The processor reads or writes each byte directly through the chip’s data register while also handling the SCSI REQ/ACK handshake. This approach is easy to understand and debug, which is why many early hobbyist and embedded systems used it, but it consumes considerable CPU time because every transferred byte requires software intervention.

For better performance, the 5380 also supports interrupt-driven operation. Instead of continuously polling the controller, the CPU allows the chip to generate an interrupt whenever a SCSI event occurs—such as a phase change or data request. This reduces wasted CPU cycles because the processor can perform other tasks until the interrupt arrives. The actual byte transfers may still be CPU-controlled, but the system becomes much more efficient than pure polling mode.

The highest-performance mode supported by the 5380 is its DMA (Direct Memory Access) mode. In this configuration, the controller cooperates with an external DMA controller—commonly an Intel 8237 DMA chip in 8086/8088 systems—to transfer blocks of data directly between memory and the SCSI device with minimal CPU involvement. The 5380 provides special DMA handshake signals and internal logic to automate the SCSI REQ/ACK timing during transfers. Once initialized, the DMA controller moves bytes automatically while the 5380 handles the bus handshaking. This dramatically improves throughput and reduces processor overhead, especially during large disk or tape transfers. However, implementing DMA is more complex because both the DMA controller and the SCSI chip must be synchronized correctly.

Another important operating concept in the 5380 is its support for different SCSI bus phases. Regardless of whether PIO or DMA is used, software must manage transitions between phases such as Command, Data In, Data Out, Status, and Message phases. The chip exposes these phases through status registers, allowing software to determine what type of transfer is currently occurring. Because the 5380 leaves much of the protocol sequencing to software, programmers have very direct visibility into how the SCSI bus operates internally, which is one reason the chip became popular in educational and experimental systems.

For this board we will design the circuit that allows the DMA mode. However most systems will not utilize the full DMA capability using a DMA controller etc.

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