Increasing the FPGA ROM to 16K.
Up until now we have been running the Z80 monitor within a 4 K boundary from F000H to FFFFH with two 4K pages either of which can be switched in or out.  This has allow us to have a fairly extensive basic Z80 monitor and a separate menu driven 4K section to access the IDE/CF card interface. It would be nice to have a similar menu for the SD card interface.   There is not enough room in 8K to fit all this.  The solution is to increase the FPGA ROM module to 16K and have up to four 4K pages.  The paging process is exactly the same as for the 2 page 8K ROM except now we adjust the address lines A12 and A13.  At the moment I'm only using three 4K pages:-

Page #0   A12 Low,  A13 Low    Output to Port 07H 00H    Contains basic Z80 Monitor                   SBC_MONA.Z80
Page #1   A12 High, A13 Low    Output to Port 07H 01H    Contains IDE menu and routines            SBC_MONB.Z80
Page #3   A12 Low,  A13 High   Output to Port 07H 04H    Contains SD Card menu and routines.     SBC_MONC.Z80

Remember the only link between the 4K pages is the jumps at the start of each module.  You cannot call one routine from one section to another. 

The changes within the FPGA code is trivial.  We just change the 8K ROM in the "ROM & RAM Interface" to a 16K ROM.  We add in one more address line (A13).
The trick however is building and loading up the .HEX file for Quartus.  
As before we load up the Wellon Programmer IDE.  This time we place the 4K modules at 0000H, 1000H and 2000H.
Hopefully these pictures are enough to explain the process. Remember to point the Quartus ROM dialog box (when asked) to the correct location of the SBC-MON2_4+4K+4K.HEX file.  If you don't alter the file you don't have to reload the .HEX file each time before a Quartus compile. The SBC-MON2_4+4K+4K.HEX is available at the bottom of this page.

The relevant Quartus .bdf file "upgrade" is Z80_FPGA17.bdf.  See the .zip file below

Here is a picture of the Z80 monitor with the 3 menus.
   

With 16K there is ample room to improve the above Z80 monitor!

SBC-MON2_16K.Zip                              (This .zip file contains the Z80 monitor and FPGA .HEX files)       (V1.1  9/4/2019)  
SBC-MON2_4+4K+4K.HEX                    (This .HEX file contains the file for the 16K Quartus ROM)       (V1.1  9/4/2019)  
Z80_FPGA17 -- (16K Rom Added)           (V1.1  9/7/2019)  



Notes.
The USB Port
There seems to be an issue with the Rx & Tx signals coming from the FPGA to the SparkFun Serial to USB adaptor.
In the KiCAD  schematic file (and the Quartus .BRD file) the pin designations are:-

FPGA Rx  = M8
FPGA Tx = K8

In some earlier .brd files they designation may be:-
 
FPGA Rx  = K8
FPGA Tx = M8

If you find you are not getting any USB port I/O from the monitor (with the IOBYTE bit0 =0),  then try switching the FPGA pin designations.
You can always test the USB port with the following Z80 code in RAM at 0H

3E 33
D3 35
C3 00 00

You should see continuous 3's on the USB port terminal.  (Remember to set  it to 9600 baud).

The sINTA Signal
Damian Wildie in Australia pointed out that there is an  issue with the sINTA status line.  U14 translates the status signals (including sINTA/F_sINTA) between the S100 bus and the FPGA. 
The direction of U14 can be switched for a Master or Slave implementation whuich is fine.  
  

 

However, sINTA/F_sINTA is also translated by U11.  The direction of U11 is hardwired as an input and its output is always enabled.  This causes an issue when using the board as a Master.
   

   
As a workaround. I have lifted the leg of U11 pin 2 so that it does not insert into the socket.

The FPGA Clock Speed
I recently discovered that the Z80 module in the Cyclone IV FPGA is capable of running at much higher clock speeds than we assigned for our earlier boards.
This board for example appears to Boot CPM3 from the CF card using a 50 MHz CLK going into the Z80 .brd module.
I found that the CLK speed can in fact be programmed to higher than the 50 MHz crystal going into the PLL01_50 multi clock generator.
The upper limit appears to be about 70 MHz.  However at this speed the is some variation in the speed of the "70 MHz" CLK signal.  It ranges/drifts from 68-70 MHz.

From this its clear that the FPGA Z80 Module CLK signal frequency is not the same as a "real" Z80 chip CLK Signal. 
I compare the width of the sOUT signal (Using the above code)  and conclude that a FPGA CLK signal of 50MHz is about the same as that of a "Real" Z80 chip running at 10 MHz.
Here are some examples:    

This page was last modified on 01/26/2022