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RE: [N8VEM-S100:1566] S100-68K-V3 Jumper Settings

Dave I am in the middle of bringing my board up.  I have so far step by step assembly notes for everybody with tests at each step. I am bringing it up as a bus master first.   Have monitor and onboard RAM working fine but for some reason all bus RAM is showing up as FF’s. Currently debugging!


There are a lot of jumpers  each of which will require a detailed explanation.  I’m am trying to get it debugged/ written up before others start into it so excuse the quick reply.


All the K’s have to do with master/slave switching. For a simple master, XFERI & XFERII just go to ground, K4 2-3 (slight bug,  to have 68K LED active bend out pin 1 of U71 and wire wrap 1,2 & 3 together).  JP13 is a carryover from the original Wilcox board and is basically now just a connection point in case one wants to hookup a external single step circuit as he had originally.  Yes always closed.


See below for others



From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of yoda
Sent: Sunday, April 21, 2013 2:30 PM
To: n8vem...@googlegroups.com
Subject: [N8VEM-S100:1566] S100-68K-V3 Jumper Settings


Hi John


I have some questions on the jumpers.   I am not quite sure what the settings should be for K1, K2, and K4 as they are new and probably have something to do with the TMA stuff.  Also it seems that JP13 must always be Closed or I don't understand the function of it.


Here is what I have come up with so far - I am going to start using as a bus master with no SMB currently in the system   I have labeled some with ?   Could you clarify or confirm them?  Thanks




J9      Open        Watch Dog Timer  ------- Closed

J10    Closed      Auto Vector enabled

J13    Open        Enable Various Interrupts

J14    1-3, 2-4     ROM at XX8000

J15    Closed      Enable Boot Feature


JB1    1-2, 3-4     Values for 28C256 eeprom

JB2    3-4, 7-8     Values for 62256 memory


JP1    Open         OV_A

JP2    Open         OV_B

JP3    Open         OV_C


Do not add this circuit until later, it’s for DMA in slave mode will explain later.

JP4    1-2            Connect to SDSB*

JP5    Open         S100 pin 65


Only if these signals are not generated by front panel or our SMB

JP6    1-2            Bus_RESET*

JP7    1-2            HOLD*

JP8    1-2            SLAVE_CLR*

JP9    1-2            POC*

JP10  1-2            BUS_RESET*

JP11  1-2            MWRT*

JP12  1-2            Clock*


JP13  1-2            ???? seems this needs to be always connected see above



Do not add this circuit until later it’s for DMA in slave mode will explain later.

JP14  Open         BR*    ???????

JP15  1-2            PHLDA*

JP16  Open        S100 pin 66


These are fine

K1     1-3            XFERI        ?????

K2     3-4            XFERII       ?????

K3     1-2            NMI*

K4     2-3            XFERII

K5     2-3            DODSB*

K6     2-3            HALT

K7     2-3            bA20  ------- 1-2


P2    dependent   Sets number of Wait States


The whole U2,U3 cascade is for handshaking on master to slave transition and DMA designation

In master mode this whole circuit can be ignored


P5    1-2             TMAXPU*      ?????

P6    1-2, 5-6      Passes Master Reset through  ????  For master P6 1-3 and 5-6 check pins carefully

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