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RE: [N8VEM-S100:2284] Re: Jumpers on Z-80 CPU Card

Hi Neil!  Thanks!  Below is the corresponding circuit in the S-100 Utility board.  The SR flip-flop is U21A and U21B.  Is U8 (74LS153) getting enabled when either the CS_PPI* or BRD_RESET* go low?  Also is 1Y0* going low?  I am wondering if the RFSH* signal is messing up the ROM/RAM chip select logic for Slot #0


There should be some sort of pulse coming out of U22A and U22B whenever there is a reset or the PPI is selected.  If not then we are hot on the trail for where the problem is located.


Thanks and have a nice day!

Andrew Lynch






From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of nbreeden
Sent: Thursday, January 23, 2014 10:47 PM
To: n8vem...@googlegroups.com
Subject: Re: [N8VEM-S100:2284] Re: Jumpers on Z-80 CPU Card


MSX2 Update.

I've been looking in detail at the Goldstar implementation Andrew based the utility board on and have some observations and thoughts on how the Goldstar MSX2 design works.


The system on power up or reset needs to be able to access the system BIOS ROM; the ROM is in SLOT Zero starting at address 0x0000. The 8255 PIO is also reset at power up or on system reset resulting in the ports being set to input; this means Port A is not configured to allow access to the BIOS ROM in slot zero; the first few bytes in that ROM configure the 8255 to allow it to control the slots.



; $0000 CHKRAM
; Function : Tests RAM and sets RAM slot for the system
; Registers: All
; Remark   : After this, a jump must be made to INIT, for further initialization.
                ; Initialize interface
                ld      a,$82
                out     (PPI_REGS),a
                ld      a,$50
                out     (GIO_REGS),a 

               ; Initialize memory bank
                xor     a
                out     (MAP_REG4),a
                inc     a
                out     (MAP_REG3),a
                inc     a
                out     (MAP_REG2),a
                inc     a
                out     (MAP_REG1),a


We thus have a chicken and egg issue. In the Goldstar design U32A and U32B are configured as a set/reset flip flop. I believe this flip flop is the key to how the system powers up; the sequence would be:




8255 ports are set to input


The S/R flip flop holds the G inputs on U27 (74LS153) high; as both G inputs are high the two outputs (1Y and 2Y) are low.


These two outputs become the select inputs on U11 (74LS139). As A14/A15 are low (these to the G inputs on the LS139) the outputs of U11 that control slot 0 are low and the system can access the BIOS ROM to run the first few instructions; these run and the 8255 is set to configure the slots.


Y5 which is generated by the C port in the 8255 as part of the keyboard scanning; this then clears the S/R flip flop; the G inputs on U27 are set to 0s and the system enters the normal 8255 controlled slot mode.


The utility board design is using the 8255 select bit to clear the S/R flip flop; I don't believe this will work as it will reset the S/R flip flop before the 8255 is fully configured.


I'll be updating my monitor to configure the 8255 as the MSX2 BIOS does and will see if I need to tweak the utility board to match the Goldstar design.





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