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Re: [N8VEM-S100:978] i960 / V96BMC ~BLAST timing
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Regarding the capacity of DRAM that the V96BMC supports.
I think you also have to account for the number banks, I think the
V96BMC supports two banks, does it not?
In any case I'm going to have to go over that again from the
beginning, and make sure I understand the various configuration
On 07/16/2012 02:55 PM, mike wrote:
> The burst-mode simply means that the processor is requesting a
> small number (usually about 4) memory transactions back-to-back,
> one on each clock cycle, without having to start from the beginning
> of initiating a transaction each time.
> The processor will assert the ~BLAST (Last cycle of the burst) line
> on the last cycle of the burst.
> I believe the DX486 was the first in the Intel family that used
> burst mode. I believe that if you look at the DX486 pinout you will
> find a ~BLAST pin.
> This is why, when using the burst-mode controller with the 386 you
> would need to have ~BLAST asserted on the first cycle of the
> memory transaction to indicate that it is both the first and the
> last transfer cycle in the transaction (in other words an ordinary
> memory transfer).
> Regarding the 64MB upper limit of the V96BMC, I was trying to sort
> that out also. Their literature claims the capability to drive
> 512MBytes of DRAM.
> Are you accounting for all the rows and columns?
> In any case, yes, I was tearing my hair out late at night trying
> to sort that out, it was giving me a headache. I'll try again with
> a clear head.
> On 07/16/2012 01:51 PM, John Monahan wrote:
>> The later/higher capacity Controller chips all seem to call bro
>> Burst mode refresh. Unfortunately I don?t understand this area
>> enough to know if that can be used with an 80386.
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