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RE: [N8VEM-S100:978] i960 / V96BMC ~BLAST timing

Thanks Mike, now I understand, makes sense. The 80386 does/can pipeline its
addresses. It has a dedicated pin "Next Address, or NA#" to indicate it is
emitting the address and status signals for the next bus cycle during the
current cycle, but I guess that is different from a 80486 burst request
where the 486 just slams down addresses back to back (and then when done)
pulls the BLAST* pin.

Really anxious to see how you do with high capacity DRAMs/conrtroller. It
really would be great to have a GB capacity S-100 board since DRAM SIMMS are
so cheap these days.  On top of that, any RAM layout would be generally
applicable to any 80386 SBC type of setup since our ribbon cable "over the
top" connection is our choice of lines.  The S-100 aspect just makes
communication/storage etc. simpler.



John Monahan Ph.D
e-mail: mon...@vitasoft.org
Text:    mon...@txt.att.net

-----Original Message-----
From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On
Behalf Of mike
Sent: Monday, July 16, 2012 11:56 AM
To: n8vem...@googlegroups.com
Subject: Re: [N8VEM-S100:978] i960 / V96BMC ~BLAST timing

Hash: SHA1


The burst-mode simply means that the processor is requesting a small number
(usually about 4) memory transactions back-to-back, one on each clock cycle,
without having to start from the beginning of initiating a transaction each

The processor will assert the ~BLAST (Last cycle of the burst) line on the
last cycle of the burst.

I believe the DX486 was the first in the Intel family that used burst mode.
I believe that if you look at the DX486 pinout you will find a ~BLAST pin.

This is why, when using the burst-mode controller with the 386 you would
need to have ~BLAST asserted on the first cycle of the memory transaction to
indicate that it is both the first and the last transfer cycle in the
transaction (in other words an ordinary memory transfer).

Regarding the 64MB upper limit of the V96BMC, I was trying to sort that out
also. Their literature claims the capability to drive 512MBytes of DRAM.

Are you accounting for all the rows and columns?

In any case, yes, I was tearing my hair out late at night trying to sort
that out, it was giving me a headache. I'll try again with a clear head.

- --Mike

On 07/16/2012 01:51 PM, John Monahan wrote:
> The later/higher capacity Controller chips all seem to call bro Burst 
> mode refresh.  Unfortunately I don?t understand this area enough to 
> know if that can be used with an 80386.

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