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Re: [N8VEM-S100:980] i960 / V96BMC ~BLAST timing
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That's interesting about the 386 NA# pin, I did not realize the 386
had that, a bit different than burst mode, but somewhat similar idea.
I'll see what I can do with regard to sorting out the DRAM controller.
I agree a high capacity DRAM setup would be outstanding.
I'm so glad now that I kept all sorts of RAM sticks of just about
In any case I like you idea of the incremental approach so you're not
trying to debug too many things all at once....baby steps.
On 07/16/2012 08:12 PM, John Monahan wrote:
> Thanks Mike, now I understand, makes sense. The 80386 does/can
> pipeline its addresses. It has a dedicated pin "Next Address, or
> NA#" to indicate it is emitting the address and status signals for
> the next bus cycle during the current cycle, but I guess that is
> different from a 80486 burst request where the 486 just slams down
> addresses back to back (and then when done) pulls the BLAST* pin.
> Really anxious to see how you do with high capacity
> DRAMs/conrtroller. It really would be great to have a GB capacity
> S-100 board since DRAM SIMMS are so cheap these days. On top of
> that, any RAM layout would be generally applicable to any 80386 SBC
> type of setup since our ribbon cable "over the top" connection is
> our choice of lines. The S-100 aspect just makes
> communication/storage etc. simpler.
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