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Re: [N8VEM-S100:1863] A new S-100 Bus general purpose 1MG Static RAM + EPROM S-100 Board.

My first cut on the "new" ver 3 S100 RAM/EPROM board

Make the chip pairs use the SAME configure jumpers
Make both pairs of chips use the SAME pin-out ie; ram or prom in either side, Support RAM on both chip pair.. 28 pin part or larger, this will allow ram or prom to be in lower or higher bank

Remove the jumpers for older and rarely used chips to make the board easy to configure. ie: remove option for chips less that 27C256, or 27C512 (ie: 28pin parts an above)
this will make addressing selection easier..

map address line for RAM using same pins as PROM...  ie: no need for matching data sheet, as Ram is not sensitive to address line mix up...
Allow for use of a battery (CR2032) on board to back up RAM as its done on ZetaZ80 with option for external battery option (3 pins... gnd.vbat.gnd) using a DS1210 (allow for two battery sources)
Support for large 39SF040 with a jumper on A18 to select high or low haft of chip, this will allow multi images in prom 
Keep small 8 bit boot rom, support 24 and 28 pin devices... allow support of using large chip up to 28C512 with hi/low select of extra address lines... to allow multi images in prom

~~ _/) ~~~~ _/) ~~~~ _/) ~~~~ _/) ~~

Tom Lafleur
(858) 759-9692

On Mon, Sep 2, 2013 at 10:08 PM, monahanz <mon...@vitasoft.org> wrote:
About two years ago Andrew and I made an S-100 bus E-PROM board that could utilize a number or RAM and ROM chips. It proved very popular. All production quality boards were quickly taken.  A second "V2" version of the board was later made. That too went quickly. 

A number of people have requested an "All in One" RAM/ROM combination board capable of working in 8 or 16 bit S-100 systems with pre or post IEEE-696 CPU boards and capable of accepting a wider range of UV-EPROMS, EE-PROMS, Static RAM chips and Flash-RAM chips.  Also in view of the range of chips and CPU's a flexible wait state circuit that can independently assign 0-8 wait states to the above chips would be desirable.  Finally, it would be nice if the EPROMs could be phantom/shadowed in or out  depending on which CPU is controlling the S-100 bus.  For example one normally would not want a Z80 monitor at F000H if the bus has given control to an 8086 in a 1MG address space.  

See here for a description of such a board:-  


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