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Seattle Computer Products --  SCP-200B   8086 CPU Board

After an initial burst of activity many S-100 boards became "me too" boards in the marketplace.  Concentrating on price and/or getting multi-board functionality on to one board.  The SCB 8086 was a significant shift in increasing the functionality of the S-100 bus.  While there were a few 8088 CPU S-100 boards appearing at the time, the SCP board really faced head on the issues of getting a 16 bit CPU on to the bus. This was accomplished, yet at the same time, making sure the board abided by the then proposed IEEE-696 guidelines.

SCP 8086 Board

The SCP 200B as it was called, had a clean design that was actually taped by a hand.

The board consisted of an Intel 8086 CPU chip with the electrical and mechanical hardware to interface it to the S-100 bus.  It could  be used to upgrade the performance of current S-100 systems by swapping CPU cards or it could form the foundation of a new 16-bit computer.

How the board handled some of the S-100 signals was as follows:

S-100 Pin 24, The Master Clock.   All timing signals were derived from an on-board 24 MHz oscillator. The clock rate of the 8086 chip itself was either 4 or 8 MHz. A lower-priced version of the board was capable of 4 MHz operation only, while the higher-priced version has switch selection of either a 4 or 8 MHz clock. All 4 MHz-only CPU cards were factory upgradable to 4/8 MHz. Interestingly, when the board first came out, the fastest generally available version of the 8086 Intel offered was 6MHz.

The S-100 bus Pin 49, is always 2 MHz. This was generated on the board.   While pSTVAL* ( pin 25) was equal to the clock frequency of the CPU (4 or 8 MHz).   pSTVAL* and the master clock were equal in phase, but pSTVAL* may be configured to be disabled (tristate) by CDSB* (pin 19) while of course the master clock was never disabled.

The 8086 allowed 3 clock cycles for memory access (minus delays and setup time). At 8 MHz, 250 ns memory is required while at 4 MHz, over 500 ns access time is allowed.  If more time is required, the card could be switched to insert a wait state in every bus cycle, SCB used the IEEE-696 pin 98 (ERROR) to indicate the clock speed t -- high for 8 MHz, low for 4 MHz. This may be used to control wait state generators of peripherals.  Clearly not not standard!

The 8086 CPU chip is a 16-bit processor which was interfaced to the S-100 bus by the support logic in either of two modes: 8-bit mode or 16-bit mode. The mode was selected dynamically at the beginning of each bus cycle, depending on CPU status and bus response, as follows:-

If the processor wished to read or write 16 bits, sXTRQ* (pin 58) on the bus was driven low. The addressed device could then respond by pulling low SIXTN* (pin 60) if it could perform a 16-bit parallel transfer. Timing for SIXTN* was the same as the READY lines (RDY/XKDY) -- it had to be valid 50 ns before the rising edge of the master clock that ends pSYNC. An exception to this was if a wait state was requested (externally or on-board), SIXIN* could be delayed until near the end of the last wait state. SIXTN* was latched on the rising edge of the master clock, either near the end of pSYNC or near the end of the last wait state, any changes after this time were irrelevant.

If, at the time SIXTN* was latched, it was high (inactive), then sXTRQ* was removed and a double 8-bit mode transfer was selected. Otherwise, sXTRQ* was kept low and 16-bit mode was selected.

Should the 8086 CPU card be used in a system which previously defined a conflicting use for bus pins 58 or 60, either or both of these lines could be disconnected from CPU logic. In this case, 16-bit mode was not possible but the board could at least in theory work in 8 bit mode.

All 24 IEEE-696 S-100 address lines were driven by the CPU card; however since the 8086 chip itself generates only 20 bits of address, A20-A23 were always driven low.

Traditionally, S-100 memory cards have decoded only the lowest 16 address lines, limiting their address space to 64K bytes. Ordinarily, use of such cards in a system with more than 64K was not possible because these cards will appear in the same relative position in each 64K block. However, special provision was made on the 8086 CPU card, selected by a jumper: Whenever a memory location ABOVE the lowest 64K is addressed, PHANTOM* (pin 67) was driven low, which may be used to disable memories with a 16-bit only address. Thus these memories appear only in the lowest 64K, when PHANTOM* is not being driven.  This  Phantom driving circuitry on the CPU card continued to function during DMA operations. Thus DMA controllers that use a 24-bit address did not have to be concerned with the presence of memories using only a 16-bit address.  This was a neat trick and very useful to people that already have an investment in S-100 memory boards.

The proposed IEEE-696 standard allowed and the 8086 CPU chip supported a 16-bit I/O address. However, traditionally the lower 8 bits and upper 8 bits of the address have been the same, and unfortunately many devices have been designed which decode their I/O address from the upper 8 lines. To maintain compatibility with such devices the support logic on the board could be jumpered to throw away the high 8 bits of the 8086's I/O address and substitute the low 8 bits to allow these old boards to work.  Clearly not a lasting situation as IO space on the S-100 bus was becoming crowed.

Soon after Intel introduced the 8086 they introduced "co-processors" to run with the chip. There were two, an 8087 math coprocessor and a less common 8089 I/O co-processor.  For scientific and statistical type applications the 8087 was quite useful in speeding up program run time.  Later SCP and many other manufactures had a spare 40 pin socket beside the 8086 for co-processors on their CPU boards.

SCP in fact had a small daughter board you could add to the above 200B board to accommodate a co-processor.  Such a setup is shown below.

SCP 8086 with 8087 board

The very detailed and thorough manual for the SCP 200B board can be obtained here.
SCP also supplied a "Zapple" like ROM monitor program to used with the board. 
The manual for this monitor can be obtained here.
Bill Machrone wrote up a brief review of the board in 1981 for Microsystems (Vol 2, #4, p22) it can be seen here.


Other Seattle Computer Products  S-100 Boards
8086 CPU   8086 Support Board   16K (24-101)RAM   16K (107A)RAM  16KRAM   64KRAM   Serial IO    DiskMaster


This page was last modified on 10/25/2013