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An S-100 8088 CPU Board.
  
  8088 CPU Board
Introduction
Having completed our 8086 CPU board there have been a few request for a simpler 8088 8-bit CPU board.  Such a board would be a nice stepping stone to a 16 bit S-100 system.  Here is such a board.  It is essential you read a description of the 8086 CPU board before reading about this 8088 CPU board.  The two boards have 90% of their circuits and logic in common.  I will only describe the construction details of the board here.
  
Step By Step Building The Board.
Since for many this board may be their first venture into putting a 16 bit system in their S-100 bus,  I will go into some detail as to how to get it up and running and while later this year and next  we will be moving up to 80286, 80386 and 68K CPU boards it is really important to have a basic S-100 16 bit CPU board you can fall back on to debug these more complicated systems.

The first step is to examine the bare board carefully for scratches or damaged traces. Use a magnifying glass if need be. The quality of the boards we get is excellent. I must have done 30 by now, never had a problem, but there is always a first time. A broken trace is almost impossible to detect by eye on a completed board.

Next solder in all the required IC sockets, resistors, resistor arrays, capacitors, jumpers, the 24MH crystal, SW3 and the voltage regulator.  Do not add the LED's or LED bar yet. Be sure you put the resistor arrays in with the correct orientation of pin 1. Check their values before  soldering (they are difficult to remove). 

For prototype boards I generally use "double swipe" IC sockets. For a critical board like this I prefer to use "Machine Tooled" IC sockets.  However they are more expensive and you have to be particularly careful not to bend the IC pins.  If you think you will be doing a lot of EEPROM burning you should use the Low Profile ZIF sockets (e.g. Jameco #102745) for the EEPROM socket.  The two clock oscillators should have their own special sockets (e.g. Jameco #133006).

Check the voltage to sockets on the board is above 5V by placing the board in your S-100 system using an extender board. With no load you will typically get 5.00V  (+/- 0.25V).  BTW, your system should boot and run correctly with its Z80 CPU. If not, you have a serious solder bridge somewhere on the board.  Before you do anything else with a magnifying glass go over every socket on the board and examine for a proper solder joint. I like to "reheat" each joint just to be on the safe side. The silk screen/varnish on these boards us quite thick. It's easy not to have a good solder joint for the ground pins.  Double check.   Extra time here will save you hours later!

We will now build the board up in functional steps. Avoid the temptation of adding everything at once and popping it into your S-100 box. Step by step is faster in the end -- trust me.

First we will add the 5 LED's.  Insert LED D7 into the board (usually the longer lead into the square pad) but do not solder yet.  Insert the board into your S-100 system and with a probe tied to +5V touch pin 3 of IC socket U66. The LED should light up. If not switch the LED leads.  Only then solder in place.  Repeat for LED's D2, D6, D5, and D3 only this time ground the appropriate pins of U66. Solder the LED's in place and recheck.

The color of the LED's is up to you. I always use blue for "board select" in my system so LED D7 is blue.  Since D2 and D6 are for wait state indications I use the same colors (yellow).  D6 is on when the EEPROM is being used so red and D3 is only active if the 8088 is in HALT mode so it is green.  Here is a picture of the board at this stage:-
   
  No IC's Yet

 
Next we will add the circuit that switches the board from a dormant state on the S-100 bus to an active slave.

Jumper P67 1-2 and 3-4 (Vert.)   and P36 1-2 (Horz, bottom). While on jumpers, please note every time when we talk about jumpers,  position 1 is the square pad of the jumper. In order to minimize board trace lengths, its actual position/orientation on the board will differ from jumper to jumper.  Sometimes they are top to bottom or left to right, other times the exact opposite.  An incorrect jumper can be a real pain in debugging a non-working board. Check with the schematic each time, to be sure . Make sure you correctly identify pin 2 in each case.

Next add IC's U52, U89, U90, U91, U49, U60,  U92, U55, and U56.

Insert the board into your S-100 system and with your Z80 monitor input port EDH.  (This will be our default port to switch out the Z80 and activate the 8088 board on the bus).  The jumper on P36 should switch from high to low.  Input again, it should go back high.  Note just in case you have port EDH assigned to something else in your system, jumper P67 also allows you to also use DDH.  Here is a picture of the board at this stage:- 
   
  handshake
          
At this point you can now add the 2 MHz Oscillator and U79. Jumper JP7 if your master Z80 CPU does not supply the 2MHz Clock signal (S-100 pin 49), when it is in  a hold state.  This is the case for our Z80 CPU Board

Next we will add the complicated but critical handshake circuitry that switches this board on to the S-100 bus as the current bus master.

Check we have the above jumper P36 1-2.  Add P57 2-4 (Horz, top of board),  JP17, JP12, K9 2-3, JP7, K10 2-3 and JP8
Next add U50, U53, U57, U59, U66.

Jumper JP8 if your master Z80 CPU does not supply the MWRT signal (S-100 pin 68), when it is in  a hold state.  Unless you are generating the MWRT signal with an S-100 bus front panel board or our SMB, install the jumper. Never have two boards putting the MWRT signal on the bus simultaneously.  It's generally best/fastest to have the MWRT signal generated on each CPU board.

Input port EDH again the LED D7 should light up. However this time the Z80 will be in a hold state and will not respond to any commands. If you are using my Master Z80 Monitor use the "W" command.

Next add the CPU clock Oscillator (initially use a low value like 15MHz). This will run the CPU at 5MHz initially. Also add the 8284, (U64) clock controller.  Note you can also use an 84C84 chip. These run faster and do not run hot like the original 8284's. Set K1 1-2 (for oscillator not crystal source). The 82C84 clock controller takes a 3X Oscillator or Crystal.  So in a final system (see below) we would use an oscillator of 11X3 = 33 MHz.  Of course you can use a slower Oscillator if you like.   Alternatively you can use a crystal with the above values and set K1 2-3.

Add U58.  With a logic probe check for a clock signal on pin 19 of socket U70 and pin 22 of socket U70 is high.   Activate the board and check pin 21 of socket U70 goes from high to low and pin 22 stays high.

Next we will add the wait state generators.
With this board you can go up to 8 wait states! More than 4 however is probably not practical.

Add U87, U88 and U81.  Jumper p65 (labeled I/O Wait 1-8) 5-6. Jumper p66 (labeled EPROM Wait 1-8) 7-8.
Repeat the above test. The LED D7 should still light up.

Next add U63 and jumpers JP 13 & 14. (Note these may be removed later if the master CPU board keeps the INT* and NMI* S-100 bus lines pulled high, see below).  Set jumper K4 2-3.  Activate the board and check pins 18,17 and 23 of socket U70 are all low.  Insert the LED bar do not solder and check the right most bar lights up. If not check the LED bar orientation and solder in place.

Next we will insert the critical CPU control and status lines circuitry.
Insert U1, U67, U68 (the 82C88) , U61, U72 and U65.
Jumper K8 1-2 (note pin 1 is on top), K12 1-2, and K13 1-2.
Jumper K5 1-2, K6 1-2, K7 1-2, K11 1-2

Activate the board. The "Halt LED, D3" should light up. See the picture above that describes the LED bar.
Here is a picture of the board at this test stage:-
    
LED D3
     
Next we will add the onboard EEPROM circuitry.  We will setup the board with a 28C256 EEPROM (but only use part of the total ROM space for our monitor code residing at F8000H-FFFFFH, see below). 

Add U80.
Jumper P62-P64 1,2,3,4,5 and P64-P63 6,7,8.

For an 28C265 EEPROM:-
Jumper K3 1-2, K2 1-2 and P2 2-3
Set SW3 1-5 open, 6-8 closed.
Activate the board, LED D5 (and D3) should light up. 

Here is a picture of the board at this stage:-
      
  EPROM Circuit

Next we will add the drivers for the onboard EEPROM
Add U85, U86, and U84. Repeat the above board activation test (input port EDH).

Next we will add the 8088 drivers.
Check pin 19 of sockets U77 and U76 are all high before adding these IC's.   If not find out why before going further. 
Add U77, U76

Next check pin 1 of sockets U55 and U56 are high (with the board NOT activated).
Both pins should go low on board activation. 
Add U55, U56

Next add all remaining IC's to the board (U73, U74, U75 and the 8088 CPU, U70). 
  
We are now ready for the big event -- let the 8088 CPU control the bus.
We have setup the 8088 CPU board above to initially act as a slave board in the S-100 bus. When we input port 0EDH the CPU will wakeup from its reset state at FFFF0H in RAM (near the top of its 1MG address space). What we have there determines what the CPU will do after a reset.

The first thing we will do is have the 8088 go into a HALT state when it gets control of the bus from the Z80 by placing the 1 byte opcode F4H at FFFF0H in its address space. There are a number of ways we can do this. 

The easiest is if you have one of our S100Computers Z80 CPU boards (or the Intersystem's Z80 Series-II board) and RAM at the top of the 1MG address space (e.g. our 4MG static RAM Board) you can place F4H in RAM at that location as follows:-

First jumper K3 2-3. This inactivates the boards EPROM circuit.

Switch into the Z80 memory space RAM at FC000H-FFFFFH -> 0H
 
QOD2,FC
F0,3FFF,F4       ;Fill the whole area with HALT's initially just to be on the safe side.

Reset the system
Enter the "W" command (This has the Z80 input from port EDH transferring control over to the 8088).

The D7 LED should come on and the 8080 CPU "HALT" LED D3 should light up.  This indicates the board is correctly reading data from the S-100 bus.  Next fine tune the above by:-

QOD2,FC
F0,3FFF,0
S3FF0,F4

Reset the system
Enter the "W" command (This has the Z80 input from port EDH transferring control over to the 8088).

If this does not happen there is something wrong with the boards ability to interact with the S-100 bus.  To debug this, it is best you initially bypass S-100 bus access and just use the onboard EEPROM described next.

To use the board's onboard EPROM for startup/debugging,  jumper K3 1-2.
We now need to program an EEPROM (lets use a 28C256) first with F4's.

There are many commercially available UV and EE PROM burners available. I use a Wellon VP280 Programmer which works well on a Windows PC  32 or 64 bit versions (some others do not).

Initially just fill the whole edit buffer with F4's and program the whole EEPROM.
Insert the EEPROM in U82 and boot the CPU.  The "HALT" LED (D3) should come on.
If it does not then chances are you have an addressing problem with your board.  Double check your SW3 switch settings, P62-64 settings and all jumper settings. 
 
One very useful trick is to pull the CPU ready line (pin 22) low immediately after the CPU returns from a reset state. In this state the address pins of the CPU (and S-100 address lines) should show 0FFFF0H.   To do this bend out pin 1 of U58 and jumper it to ground with a wire clip.  Activate the board (via your Z80).  If you have our SMB the S-100 bus should show 0FFFF0H.   If not, starting from the CPU follow each line to the bus to identify the problem.

Do not go further unless you can get the CPU to Halt with a EPROM of F4's first.

Next we will but a simple program in a PROM and have the CPU execute it.
We will write a very simple routine to continuously output a character ("3") on the CRT.

(B0, 33, E6, 01, EB, FA)
START:  MOV    AL,33H
              OUT    01H,AL
              JMP     START


If you are using the above Z80/RAM substitution approach you can type in the few bytes by hand to address  00FFFF0H.

From the Z80 Master monitor use:-

QO D2, FC                               ;Temporally allow the Z80 to access RAM at FC000-FFFFFH at 0-3FFFH
S3FF0  B0,33,E6,01EB,FA         ;Insert the above code at FFFF0 in RAM
QI ED                                      ;Inputting port ED activates the 8088.

If instead you are booting from the onboard EEPROMs you need to "burn " a prom.   You need to assemble the short 3 line program above with an origin at 0FFFF0H. 
 
For the Weldon VP-280 type programmer, load the .BIN file.  "From File HEX address" leave as 0000. For  "Buffer Address"  put in FFF0. Do not change "File Size (HEX)".   

Once the 8088 gets control of the bus it will continuously display the letter "3" on the screen.
If you achieve this you are well on your way to getting the system going. 

If not and you have the SMB S-100 front panel board, use the reset/ready trick described above to lock the CPU at 0FFF0H. Flip the SMB stop switch on, remove the ready clip connection on pin 1 of U58 and on the SMB single step the CPU forward all the time monitoring the bus address displayed.  This may help locate the problem. 

Remember however if you are single stepping through the onboard EEPROM, the SMB Board Hex display will NOT display the correct data.  This is because the onboard EPROM data goes directly to the 8088, not over the S-100 data in bus.  (You will actually see data in RAM at that S-100 location). Address lines and status lines of course are correct.

Next you can burn the entire 8086 Monitor program in a single 28C256 EEPROM.
Reboot the board. The monitor should sign on and the "K" command should display its main menu:-
  
  K Command
  
 
Bringing up a 8086 Monitor,  CPM86+ and MSDOS with this 8088 S-100 Board.
To be of any use we clearly need a disk operating system to work with this board.  There are really two options: CPM86 or some type of MS-DOS. I have used both in the past.  However again realizing this may be a dramatic step for people coming from the 8 bit world, I will start with a 8086 Monitor for the onboard EEPROMS and then "do" CPM86+.  Please click here to get to the 8086 Monitor software section of this web site for the 8086 Monitor details,  or the CPM86+ section for step by step instructions about bringing up CPM86+ on a CPM(80) system for the first time. 

Much work has gone into writing the 10,000 line 8086 monitor code so it is compatible with MSDOS.   As it currently stands the 8086 monitor below will allow you to boot MSDOS v4.01 from our ZFDC controller board and/or IDE CF card board unaltered as they are supplied by Microsoft using this board.   A description of this is given elsewhere here and really requires you study the monitor code itself in some detail.

Link to 8086 Monitor and Video Describing the Board & booting MSDOS with it.
Link to CPM86+

PROM JUMPERS
The board schematic shows a 27C512 UV EPROM.  If you are using one of these PROMS you can use its full 64K of memory space, (normally FF000H to FFFFFFH) by jumpering P2, 1-2 and K2, 2-3.  This gets the address line A15 to pin 1 and A14 to pin 27. 

There is no 28 pin equivalent 512K EEPROM chip. 512K EEPROM chips are 32 pin chips.  There are however common 28 pin 256K EEPROM chips (28C256's).  You need to be careful with Jumpers K2 and P2 however. For a 28C256 jumper pin 27 (the programming bit) is set high, so K2 1-2. Be sure it is not connected to A14. Otherwise the code in the EEPROM will get scrambled.  Pin 1 goes to A14, (P2 3-4).

This unfortunately limits the ROM space to 32K.   Still plenty of room. However my 8086 Monitor has now grown larger than 32K. You can still squeeze it into a 32K chip if you do not add the IBM-PC character set which is seldom used.   

Note in this configuration the 32K monitor on this board will reside and appear at F0000H and F8000H.  Only the F8000H location is used.  The 8086 monitor code has an equate "OFFSET_8088" to make sure it is assembled for this location. If you use the larger 25C512 EPROM of course the monitor should be assembled to run at F0000H (as for the 8086 board).  Be sure to read about programming these chips at the start of the code documentation.  Properly done, the start of the ROM at 0H should have an EB byte (along with other Jumps into the monitor code).


Speed
Even though the 8088 CPU was sold by Jameco as an 8MHz CPU (#52169),  I find that I could run the board in my system at 11MHz (Using a 33MH Oscillator).  This is in a 22 slot motherboard with active termination and about 10 S-100 boards resident.  Note I use a 82C84 and 82C88 clock and bus controller as well as a number of 74Fxx chips as illustrated in the schematic.   I used no  I/O wait states and 3 EPROM Wait states. The 82C84 & 82C88 can be obtained from Unicorn Electronics (a great source of chips, BTW).  For jumpers approximate values for example for the sOUT (U56 pin 3), jumper p66, using a 33MHz Oscillator:-

0 wait states (no jumper) = 333ns, 1=416ns, 2=541ns, 3=625ns, 4=750ns, 5=791ns, 5=916ns, 7=1uS, 8=1.08uS.


A Description of the Board Jumpers.
The  board contains a number of important jumpers that determine how it functions. Most will not need to be changed once the system is running but it is very important they are configured correctly.  In no particular order:-
   
Jumper    Function 
JP5,JP6,JP4,JP9 Used only if the board is to act as a bus master.  Generates Power On reset etc.
JP12 Use only if no other board on the bus pulls up the S-100 HOLD signal
JP11 Use only if no other board on the bus pulls up the S-100 HLDA signal
K9, K10 Normally 2-3. Use 1-2 if board is a bus master.
JP7 Use only if no other board generates the S-100 2MHz clock signal when the 8088 is active
JP8 Use only if no other board generates the S-100 MWRT signal when the 8088 is active
P65 Sets number of wait states for onboard EEPROM (0-8). I use 3 wait states, so P65 5-6
P66 Sets number of wait states for bus I/O and INTA cycles (0-8). I use 2 wait states, so P66 3-4
P57 Normally set 2-4. Use 1-3 if board is bus master
K8 Normally 1-2. If set 2-3 control signals appear on bus a little before pSync ends.
P13, P14 Use only if no other board on the bus pulls up these signals
P36 Determines what S100 TMA line activates this board.  (Normally TMA0* from SMB, so P26 3-4. For onboard activation use 1-2 & 3-4) 
K4 Normally 2-3. This controls the 8088 special test/debugging pin
K1 1-2, Oscillator supplies CPU clock. 2-3 Onboard crystal supplies clock
K3 Normally 1-2. If set 2-3 the onboard EEPROM circuit is invisible to the 8088.
K2, P2 These pins must be carefully selected for different EEPROM and EPROM types (see below)
P67 Normally 1-2 and 3-4. This selects the port to activate the 8086 board on the bus.
P62-P64 & SW3 This selects where the onboard EEPROMS will reside in the CPU's 1MG address space
P56 1-26 These jumpers are to pull up the S-100 bus Interrupt and DMA lines IF no other board on the bus pulls them high.  Normally they are not jumper (they are pulled up by the Z80 master CPU).  It is essential multiple boards do not pull them high.
K12 Determines how the S-100 bus sWO signal is generated.  Normally 1-2
K13 Latch or unlatch the 8088 S0,S1,S2 signals. Normally 1-2.
K5,K6,K7,K11 Determines if S-100 bus status signals are latched. All normally 2-3, (Some Godbout RAM boards actully req K5 2-3).
JP1,JP2, JP3 These are jumpers that allow you to utilize extra board ground lines as defined in the IEEE-696 specs.  Nor required, do not use with older S-100 systems
  
Here is a picture of the board with the important jumpers illustrated:-

Configuration Setup  

I am currently running the above board with a 33 MHZ Oscillator yielding a 11 MHz bus clock!  This is probably at the upper limit of the S-100 bus and will only be possible in a properly conditioned/terminated bus. For this speed p66 must be jumpered 2-3 for 28C256 EEPROMS.

Also remember while all the above jumper settings describe a configuration where this board is a "slave CPU" in the S-100 bus. The board can also be configured as the only CPU in the bus or as a bus master.   The configuration is fairly obvious but if somebody cannot figure it out drop me an e-mail. 

Finally, I recently noticed that several old 8 bit S100 (non -IEEE 696) RAM boards do not work correctly unless K5,6,7 and 11 are positioned 2-3.  If possible try and use/obtain our very fast 4MG Static RAM board. The later Godbout/CompuPro boards also work well. For example the RAM 16 or RAM 21 boards.  The Fulcrum boards such as the Fulcrum "Omni 256" or the BG Computer 256K board are also excellent/fast static RAM boards.

A Production S-100 Board
Realizing that a number of people might want to utilize a board like this together with a group of people on the  Google Groups S100Computers Forum, "group purchases" are made from time to time.  Contact and join the group if you would like to be involved in this project.  See if bare boards are available and/or see if you and others may be interested in doing another board run.

Bugs.
No bugs have been reported for this board currently.  However remember if you are using the onboard port (EDH) to activate the board be sure you jumper P36 1-2 & 3-4.  This is because other boards may be expecting the TMA0* line to be low when this board is active.   The onboard port alone will not lower the TMA0* line. 


S100 Bus Master/Slaves.
Please note this board is normally set to act as an IEEE-696 bus slave.  It should work with our Z80 CPU board described on this site. It is important to remember however that this 8088 CPU board is counting on the fact that when the bus master to relinquishes control of the bus to a slave device, the bus master inactivates all of its address, data, status and control lines while the slave has control of the bus. The S100 bus signals ADSB*, DDSB*, SDSB* and CDSB* are expected to all go low as specified by the IEEE-696 protocol.  Some older S100 bus Z80 boards driven boards may not do this.

This board can configured as a stand alone bus master. However it does not have the above ability to inactivate all of its address, data, status and control lines while the slave has control of the bus.  (It's counting on the slave to lower the S100 bus signals ADSB*, DDSB*, SDSB* and CDSB*).  This is a slight limitation on this board. It has been corrected in our 80286 and higher CPU boards.

The links below will contain the most recent schematic of this board.
Note, it may change over time and some IC part or pin numbers may not correlate exactly with the text in the article above.

MOST CURRENT 8088 CPU BOARD SCHEMATIC  (V1, Final, 7/26/2010)
MOST CURRENT 8088 CPU  BOARD LAYOUT  (V1, Final, 7/26/2010)
BOM For This Board   (Rick Bromagem  (12/26/2015)
Most current KiCAD files for this board              (S100 8088-002.zip   11/5/2014)



Other pages describing my S-100 hardware and software.
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This page was last modified on 05/14/2016