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Re: [N8VEM-S100:986] i960 / C ~BLAST timing

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Don't PATA interfaces transmit data over flat cable > 12 inches in the
33MHz range?

I dunno, I just can't seem to see a one inch jumper as being that big
of an issue. I think at most we may have to do a multi-layer board. I
think if we keep the critical traces short, and take care on the
layout regarding the critical signals, I don't think there will be any
serious problems.

I've enclosed a document which is an Intel application note that covers
a lot of this stuff, and specifically relating to the 386 and 486.

One interesting passage is "2.2 Transmission Line Effect" where it
covers some rules of thumb and micro strip lines.

I think in worst case regarding the board interconnect, we may have to
use some kind of impedance matching termination like those discussed
on the Intel App Note pages 9 and 10.

- ---- V96BMC / DRAM research ------

Regarding the V96BMC chip, I think I have a very good handle on it now.

The chip can support 2 x (32 bit wide) banks of 64MBytes each for a
total of 128MBytes per V96BMC chip.

I think this is pretty good. I don't think we're going to find a
better solution that will work with '386 era parts in a chip that
still has pretty good availability.

Where they get away with saying the chip can support 512MByte
subsystem is that there can be 4 x V96BMC chips on the same bus for a
memory subsystem total of 512MB.

The 512MByte limitation comes in to play at the configuration
registers. There are 3 pins (ID0 - ID2) which determine the address of
the configuration register such that each V96BMC on the bus has it's
configuration registers placed at a unique address. There are two
words of configuration registers, thus the 3 bits of Chip ID address
instead of two.

So a 512MB DRAM card built around this chip would look like this; 4
V96BMC chips, 8 sticks of 64MB 72-pin SIMMs (I think the 72 pin simms
are looking like the most likely to be compatible with this arrangement).

That's probably about all that could physically fit on an S-100 card
in any case once you add in the power supply and the bus logic.

In addition I also discovered that the National Semi NSBMC096 chip is
the same as the V96BMC chip, and also the National Semi data sheet is
more clear on several topics, and has a practical application example
that is very useful, I've attached that for your reading enjoyment.

- --Mike

On 07/17/2012 01:16 AM, John Monahan wrote:
> Darn this thing is beginning to get complicated!  Can anybody give
> a guess what the max 80386 clock frequency  we could expect with
> say a 1" long ribbon cable connecting two boards with say two IDC
> type sockets (100 connections) on each board.  For such a short
> length of "cable" is 33Mhz out of the question to address DRAMS
> with 74ASxxx drivers on one or both ends.
> John

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