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Processor Technology   48KRA-1    48K Dynamic RAM
This looks like a 64K board without one row or RAM chips. However the manual also shows the absence of this 16K or RAM. If anybody knows why the RAM chips are missing (as well as a few others on the bottom right hand side) please let me know.

PT 48K RAM    

The 48KRA-1 was designed to operate in the Sol S-100 bus and a number of other 8080-based computers which have a 2 MHz PHASE 2 rate without imposing wait states. Lines interfacing the S-100 bus are fully buffered.

Address allocation was switch selectable. The 48KRA-1 was organized into three pages of 16.384 bytes each. Each page may be independently assigned to any of 16 starting addresses at 4096-byte intervals, starting with address 0000H. If the starting address is D000, E000, or F000, that part of the page which would fall beyond FFFF is assigned to memory space in the range 0000-2FFF. (Refer to Table 3-1 in the manual, 48KRA-1 Address Switch Selection.)
A wide variety of extended addressing schemes are available as user options. Modifications for 16-bit data words can also be made by the user.  The board had IEEE-696 features like extended addressing and SXTN and SXTRQ recognition etc.  The board also recognized the Phantom line of startup.
 The board did not have a LSI Dynamic RAM refresh controller. The manual goes to great length to explain how the board does RAM refresh using the S-100/8080 clock2 signal.  It's unclear to me if this board would work reliably with faster Z80 (or greater) CPU boards.

Paul Mc Neill sent me the following information about this board:-

The three 16k pages (48k total) of populated memory chips on the board can be independently mapped over the normal 64k memory range of most S-100 computers using 16 address bits (section 3.2.2 of the manual) and only 8 data bits. The unpopulated 16k bank has to be left unmapped on the board as this is where you would have your EPROM mapped (on a different board) with the system monitor program, BIOS or boot loader program so that the addressing does not conflict with the addressing of the three 16k pages of dynamic RAM.

Sheet 1 of the schematic appears to be incomplete so I can't really decode all of the addressing options.

S-100 systems are capable of using up to 24 address bits which would allow for a total of 16 megabytes of memory to be mapped onto a system. This is where the empty bank of memory chips (U25-U32) and the empty sockets at U64 to U68 come in. U64-68 provide for extended address selection (see section 5.6 of the manual, unfortunately it appears to be incomplete) using the address lines A16-A23 so you can then populate the fourth row of dynamic RAM for a total of 64K of memory on the board. Then you could have a number of memory boards mapped at unique 64k intervals or 'banks' or 'pages'  so they would not conflict with each other.

S-100 systems are also capable of up to 16 data bits - that is what "Area A" on the board is for - so you could add jumpers to have the data bus on the board mapped onto either the 8 upper or 8 lower data bits. It may also be possible to set the board up to manipulate all 16 data bits concurrently, but I can't tell without sheet 1 of the schematic.

The manual for this board can be obtained here.


Other Processor Technology S-100 Boards
4K RAM   8K RAM   48K RAM    16K Dynamic RAM    1702 EPROM     3P+S    CUTS    GPM   VDM-1    Helios-II FDC


This page was last modified on 10/25/2013