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DAZZLER II Video Board.
One of the most spectacular early S100 boards was the Cromemco Dazzler Video Board. The Cromemco TV Dazzler was originally developed as a display device for the Altair Cyclops version of the Cyclops camera developed by Terry Walker.  The history of the development of the Cyclops cameras and the TV Dazzler is given here.  The TV Dazzler was the board that first got many of us building S100 bus computers. The graphic display that could be obtained even on a color TV set with less than a few hundred lines of assembly code was captivating. There were reports of traffic being jammed in NY city because of people looking at the display in a computer store window.  A first personal account of this event is in Stan Veit's book on the history of personal computing found here and here

Good and all as that dual board set was there were limitations.  Because it used DMA to shared the bus RAM there were serious limitations with what RAM and CPU boards it would work with.  It was made long before the IEEE-696 was adopted.  It would not work with CPU's above about 4MHz under any circumstances.  It put out a Composite Video signal only so a modern implementation would not work with a VGA monitor for example.  What is needed is a modern implementation.

With the help of Terry Walker (the original TV Dazzler designer),  we have made a new Dazzler S100 board which we call the "Dazzler II Board".  Unlike the original dual set of S100 boards this board in completely implemented on a single S100 board.  Terry did all the heavy lifting for the conversion of the original 74xx chip logic into 3 CPLD's.   The board utilizes a dual ported CY7C135 static RAM chip so no bus DMA requests are required.  This allows the board to work with a 10MHz Z80 CPU with no flickering/snow on the screen.  The board has onboard circuits to generate four different video output formats: RGB standard rate video, RGB VGA rate output, YPbPr component output, and composite video output with sync and chroma.

Cromemco later supplied another S100 board, (the D+7A I/O Converter board), to provide joystick input for programs running on the Dazzler.  Two joystick inputs are provided, each supporting an XY joystick box with 4 switches to match the Cromemco JS1 joystick operation. 

Here is a picture of this board:-
  Dazzler II Board (Final)

The board utilizes two AT1508 84 pin PLCC socketed CPLD's and one smaller 52 pin PLCC socketed AT1504 CPLD.  The latter, CPLD (U6), is actually only required if you need Composite Video output.  The remaining 52 pin PLCC chip is a dual ported static RAM chip.  The actual 74LSxxx chip logic on the board is minimal.  With the bulk of the remaining circuit devoted to the analog video signals.  In spite of its apparent visual simplicity the board is actually quite complex. Great care was taken to have minimal analogue signal paths and good power line distributions.

The Circuit
Terry Walker has written up a detailed Theory Of Operation for the board which can be seen here.

Briefly, the circuit is based on the original Dazzler concept.  512 bytes or 2K of RAM is utilized for display memory.  This RAM can reside anywhere in the Z80/8080's 64K address space and is set in software (see below). This Dazzler II board actually utilizes the full 16MG addressing range (A0-A23) of the S100 bus,  so in theory it can also be programmed with any of the 8086 - 80486 family of CPU's.  The upper address lines are set with SW6.  These are normally all low (i.e. SW6  settings are all closed/ground) so we address RAM is in the lowest 64K address space.

Note, unlike the original Dazzler, this board has its own dual ported RAM.  Z80 RAM writes will go to the boards own RAM and the corresponding RAM "window" on the S100 bus.  Z80 RAM reads however will always come only from the S100 bus RAM.    For this reason software should always initialize/fill the S100 bus RAM "window" with the boards RAM upon startup so any later RAM reads of the bus RAM exactly corresponds the boards RAM.     Most legacy Dazzler software initializes the video RAM area if Z80 RAM reads are later required. 

Since the original port 0EH DMA address data is used only to move the dual port RAM in the main bus address space, it is important that the DMA address is set before the TV Dazzler display area is written.  If the DMA address is sent after the memory is written, the displayed video image will not match the image stored in the main bus address space memory.  This is the only incompatibility with the original TV Dazzler. If desired, the port 0EH bit 7 may be left low while the memory is written with a new pattern so that the display image is blanked. 

The board utilizes two I/O ports for configuration. The default/legacy ports are 0EH and 0FH (0000111xH).  Both ports (together) can be changed with SW4. Note A0 is not used. Also for IEEE-696 port addressing,  bit 7 is the input for the address lines A8-A15 using SW5.  These are normally all low (i.e. SW5  settings are all closed/ground). 

The joystick ports are set with Switch SW3.  The default ports are 18H to 1CH (00011xxxH).
Note, ports on the original D+7AI/O board not used by the two joysticks are not implemented on this board.

Switch SW1 is an for a user defined 'extra port' .  Bits 0,1,and 2  (U18) can be used in software to configure a second page of display RAM or use a second color map table. These are describe below. They are not found on the original TV Dazzler.
Here is a picture of the default port switch settings. All the switches are closed except the 3 of SW4 and 2 on SW3 shown below in the default configuration of this board.
Switch Settings
Port 0EH hex out contains an offset address used to set the base memory address for the top left corner of the display, and the display output enable bit. Bits 0 through 6 are address offset values A9 through A15 for the display starting address. In the original TV Dazzler this formed a 7 bit binary offset which set the start point for the DMA memory read operations to fetch the display data. 

In this new Dazzler II, these bits are subtracted from the S100 memory address A15 - A0, and if the result is between 0000 and 0FFF hex, this address is used for writing the S100 data into the dual port memory on the TV Dazzler II. If underflow occurs or the result is over 0FFF hex, then the memory is not written and the data is ignored. As we mentioned above, if a read operation occurs on the S100 bus at any address, the TV Dazzler II ignores this request, and the data read by the CPU comes from the main memory being shadowed by the TV Dazzler II. Note that to obtain display of data written to the offset address range 0800 hex through 0FFF hex, it is necessary to send a H level (or set the jumper) for the Page control bit described below. The Page bit is then used as the dual port memory address bit A11 for data readout for display. Bit 7, the MSB of this port, turns on the display output if it is written to a one or high level, and turns it off if written as a zero.

Summary of Port 0EH & 0FH bits
Port 0FH out has 7 bits which are used for various functions.
Bit 7 is not used.
Bit 6 is High for a bit map display, and Low for 4 bit color or B&W pixel display
Bit 5 is High for a 64 by 64 pixel display, and Low for 32 by 32 pixel display
Bit 4 is High for a color display and Low for a B&W gray scale display

When bit 6 is High, then bits 3 to 0 are used to set bit map display appearance
Bit 3 is High for high intensity color or MSB (weight 8) of gray scale
Bit 2 is High to turn on Blue color or weight 4 of gray scale
Bit 1 is High to turn on Green color or weight 2 of gray scale
Bit 0 is High to turn on Red color or weight 1 of gray scale

Port 0EH input has 2 bits of data
Bit 7 is Low for odd display lines, High for even display lines being output. It comes from the display readout address bit A4.
Bit 6 is Low for 4 milliseconds at the end of each display frame. It comes from the vertical unblank signal, High during display time.

Port 0EH out has 8 bits of data
Bit 7 is High to enable the display generation, Low to blank the display video output
Bit 6 through bit 0 are the display memory readout base address for the pixel in the upper left corner. The memory addressing function for the display readout  is implemented with hardware external to the CPLD.

Port 18H out has 3 bits of data to control functions not on the original TV Dazzler if U18 is installed.
Port 19H out has 8 bits of data for the Joystick 1 speaker analog drive
Port 1AH out has 8 bits of data for the Joystick 2 speaker analog drive

Port 18H in has 8 bits (2X4) of data from the 2X4 joystick buttons.
Port 19H in has 8 bits of data for the Joystick 1 X axis
Port 1AH in has 8 bits of data for the Joystick 1 Y axis
Port 1BH in
has 8 bits of data for the Joystick 2 X axis
Port 1CH in
has 8 bits of data for the Joystick 2 Y axis

The digital signals for ports 19H through 1CH in and out are two's complement representations of the bipolar analog signals associated with each port.  The analog voltages are -2.5 to +2.5 volt range for the inputs (DC coupled) and -2 to +2 volts for the outputs (AC coupled).  The negative limit is 80H, midrange (0V) is 00H, and the positive limit is 7FH.

The maximum analog input voltage which should be applied to the ADC inputs is +/- 5 volts.  The ADC inputs are high impedance, and the DAC analog outputs are from a 1K ohm source with filtering to restrict the bandwidth to the 100Hz to 4 KHz range with a 10K ohm load.  A PWM DAC operating at 40 KHz is used for the analog outputs.

Joystick pinout on J11 and J16:
Pin          Signal
1           SW1 (top) Low if pressed, JS1 = port 18H in bit 0, JS2 = port 18H in bit 4, H is +5V from 10K source
2           SW2 Low if pressed, JS1 = port 18H in bit 1, JS2 = port 18H in bit 5, H is +5V from 10K source
3           SW3 Low if pressed, JS1 = port 18H in bit 2, JS2 = port 18H in bit 6, H is +5V from 10K source
4           SW4 (bottom) Low if pressed, JS1 = port 18H in bit 3, JS2 = port 18H in bit 7, H is +5V from 10K source
5           +5V from TV Dazzler regulator, used by speaker drive amplifier and JS power converters if present
6, 8, 10    Analog ground for joystick X and Y outputs and audio input
7           Joystick X output +/-4V maximum with Parallax 27800 control and standard resistors
9           Joystick Y output +/-4V maximum with Parallax 27800 control and standard resistors
11          Audio signal +/-2V to speaker amplifier input, joystick box load on signal source is 20K ohms
12          Ground return for +5V power used by speaker amplifier
13          +16V from main bus for regulator in joystick box
14, 16      No connection on TV Dazzler
15          -16V from main bus for regulator in joystick box



The Parallax 27800 joysticks have a mechanical limit which restricts the movement to a circular pattern.  For this reason they are scaled to give a +/-4V maximum output so it is possible to reach the corners such as +2.5,+2.5.  Other joystick units may not have this restriction, in which case it may be desirable to change the resistors R8 and R14 in the joystick circuit from 100K to 15K ohm, giving a +/-2.7 volt maximum output.  This will produce better resolution for the controls.

In addition to the above original control ports there are several functions controlled by jumpers located on the PC board.
A signal is High if a jumper block is not in place. These signals are normally not need to run the board and are only there for further development/debugging.

Mode 1 High for composite and YPbPr component TV display output signals, J9 p33.   Low for RGB TV and RGB VGA display output signals

Mode 0 High for composite TV and RGB VGA display output signals, J9 p35.   Low for YPbPr component TV and RGB TV

Page High to display second half of dual port memory (A11 = H), J9 p31.    Low for original Dazzler addresses (A11 = Low)

Syinv High to make Hsync and Vsync outputs positive going, J9 p 29.   Low to have Hsync and Vsync outputs negative going (VGA & TV standard)

Syall High to put negative going composite sync on all 3 video outputs in RGB TV mode, J9 p 27.   Low to have composite sync only on green output for RGB TV monitors

pt0Fb6 J9 p25 through pt0Fb0, J9 p13.  These are the inputs for port 0E hex above.

pt0Eb6 J9 p11 is the port 0E hex input data above.  This can drive a TTL load.

pt0Eb7 J9 p9 is the port 0E hex input data above.  This can drive a TTL load.

Dispen High to turn on the video generation.   Low to blank video output, J9 p5 is the dispen bit from port 0E hex bit 7 output data.

J9 p3 is a spare for future use.

Disptest High to send the internal test pattern to the display to check connections, J9 p1.   Low to display contents of the dual port memory in a TV Dazzler format. Leave this jumper off, this jumper is in parallel with the user display test switch on the top board edge.

All of the above signals have 50K ohm pull up resistors to +5V. It is only necessary to remove the jumper plug to ground for any particular signal to cause the signal to be a logic High value. The signal inputs are compatible with TTL voltage levels and do not have to be driven by CMOS.

Test point terminals are provided on various signals of the PC board to enable easy test of voltages which will indicate the circuit performance. In addition, extra test points are connected to some of the CPLD spare I/O pins. These I/O pins are connected to various CPLDs  to signal points of interest to enable verification of the circuit operation and to enhance the ability to debug the logic.  They are not normally used.

The design has separate programming connections for each CPLD. We felt that  this is a better strategy than daisy chaining the CPLDs for programming. Separate connections has the advantage that it is not necessary to reprogram the devices which don't need to be changed, and therefore reduces the chance of making mistakes on the CPLD programming sequence and history. Also, even though a single crystal oscillator could be used for both the display and signal generator CPLD devices, we provided two oscillators since the bus interface needs a different operating frequency for the analog to digital converter circuits.

Layout of the board is straightforward. A two layer board was used taking care for proper ground distribution. Note that the large chips and small parts are arranged the same way as drawn on the schematic for U1, U2, U3, U6, and the video output circuits, this way the trace work is relatively free of a large numbers of vias and crossovers. This permits making the back side of the PCB the foremost the provider of large (0.1 inch), trace work to connect important ground points into a mesh structure. Most trace work is on the front side using 5 mil traces and 10 mil spaces except for power lines, which are 20 or 50 mil line width depending on the destination and length. The incoming +5V line from the main bus is a 0.1 inch trace width to distribute power to the various board regions. A front and back ground fill was used on the final board.

U1 and U6 are closely located and rotated as shown to minimize problems with distribution of the high frequency clock signals between them and the clock oscillator X1.

For best accuracy 1% tolerance resistors should be used in the video DACs, but in actuality the closest standard 5% resistors will probably give entirely suitable operation.

In the S100 bus a simple 3 terminal low power regulator (LM7912) is used for a -12V supply. The 5V (Vcc) supply can be a LM7805 (1.5A,  Jameco #924633) or better, a Pololu 5 Volt , 2.5 Amp D24V25 Switching regulator or EzSBC 5V 3A switching regulator.  

Note if you are testing the board in the S100 bus (which supplies +8 and -16V) you do not need the power converter P19 (a CME0512C).  It's only there to test the board with no S100 bus using only a simple 8V power supply. With K4 jumpered 2-3, the CPLD's and video circuit can be tested with a test pattern just by connecting the board to a 8V power supply (see below),  i.e. no S100 bus connections. In the S100 bus K4 is always jumpered 1-2. the CME0512C is actually not needed.

The two crystal oscillator sockets have pinouts to allow both full size (14/4 pin) and half size (4pin) oscillator units to be used for versatility. The 28.636 MHz oscillator is conveniently available only in a 1/2 size plastic DIP housing, but there may be a need to use other oscillators in test which come in the full size can package. The inductors may be any convenient small ferrite bead-on-wire chokes (typically 1/8 in by 1/8 in). All resistors are best chosen to be 1/4 watt standard modern carbon film types. The transistors should be standard 2N or PN types in a TO92 package (EBC pinout, 0.1 in spacing).

There is a small configuration switch at the top of the board (to the left of the VGA connectors) for testing. If it is positioned to the right, the board will ALWAYS display the following test pattern:
  Test Pattern
The board comes up in its default color mode.
If you do not see this pattern check your board for jumper errors (see below)  or bad solder joints. 

The VGA video output circuit is fairly straightforward.  Here is an example (for the Red gun).
 Video Circuit

The board has two VGA connectors on top.  One is a standard 15 pin female PC style VGA socket for quick connections.  The other, P7,  is our own standard internal VGA connector used on all our other boards (e.g. VGA board, Lava video Board etc.) where we run a ribbon cable for video to a connector at the back of the box.

The board has the core circuit of the Cromemco D+7A I/O board.  For games two Cromemco joystick units must be constructed.  They are connected via a ribbon cable to P11 and P16 on the top LHS of the board.  Be sure to install the joystick cables with the red stripe at the left as viewed from the component side of the board.   A description of these joystick units will be provided below.  Here is the relevant circuit on the Dazzler II board.  Remember: THE JOYSTICK CABLES SHOULD BE CONNECTED OR REMOVED ONLY WHEN POWER IS OFF DUE TO THE PRESENCE OF +/-16V ON THE CONNECTOR FROM THE BUS.  A voltage transient could damage either the joystick or the TV Dazzler circuits.
 Joystick input

The core logic of the board is contained in the two Atmel ATF 1508AS CPLD's U3 and U1. They interface with the dual ported RAM (U2, a CY7C1350G), and the S100 bus to produce the digital video output signals for the analogue video section of the board.
  Board layout
The CPLD code in U3 and U1 is very complex.  It was generated by converting the original TV Dazzler 74LSxx circuit to Atmel's WinCUPL code
.  This code was the extensively fine tuned to yield efficient code that would fit in two 1508's.  Built into the code are various video test patterns to debug the board.   For most users it's best to look upon U6, U3  and U1 as "black boxes".  See here for more information about the CPLD code.

BJL_VER4.JED is the code to program the 1508 CPLD, U3.              
DISPLAY_FINL4CS.JED is the code to program the 1508 CPLD, U1.

To be compatible with the original Cromemco TV Dazzler the board can also output a composite video signal on the connector J2 pin
1,2 & 3.
For composite video however you need to add the  smaller 44 pin 1504 CPLD, U6.  (Note for standard VGA video output this CPLD is not required). U6 digitally synthesizes the composite encoded color information.

DISPLAY_FINL3DS.JED is the code to program the 1504 CPLD, U6.

Video output connection J2: This connector is pinned out to work correctly with a standard VGA display.

pin       signal
1         Red, Pr, or composite video from a 75 ohm source.  0.7V P-P into 75 ohm load with 0.3V negative sync when used.
2         Green, Y, or composite video from a 75 ohm source.  0.7V P-P into 75 ohm load with 0.3V negative sync when used.
3         Blue, Pb, or composite video from a 75 ohm source.  0.7V P-P into 75 ohm load with 0.3V negative sync when used.
6         Ground return for pin 1 for coax.
7         Ground return for pin 2 for coax.
8         Ground return for pin 3 for coax.
5, 10     Ground returns for pins 13 & 14.
13        H sync from a 75 ohm source. +4V baseline open circuit, 0V negative going sync pulses normally.
14        V sync from a 75 ohm source. +4V baseline open circuit, 0V negative going sync pulses normally.
H and V sync pulses may be made positive going by putting a jumper on P18 pin 29-30.

When the TV Dazzler is outputting B/W video (mode 0 0), pins 1, 2, and 3 are independent copies of the same video signal, and composite sync may be put on all three outputs by installing jumper P18 pins 27-28.  If this jumper is not present, then only the output on J2 pin 2 will have composite sync.

When the TV Dazzler is outputting RGB video (mode 0 0), the sync waveforms are at standard TV rate and are present only on the G output unless a jumper is placed on P18 pins 27-28.  The H and V sync outputs may optionally be used by the display if desired.

When the TV Dazzler is outputting RGB video for a VGA display (mode 1 0), the RGB outputs are 0.7 V P-P and do not have any sync.  The display uses negative going sync from the H and V outputs.

When the TV Dazzler is outputting YPbPr video (mode 0 1), the Y signal will have composite negative going sync on it.  The Pb and Pr signals, being bipolar, will have a 0.65 volt DC baseline offset into a 75 ohm load.  This works satisfactorily on most component displays.

When the TV Dazzler is outputting composite video (mode 1 1), then composite sync, burst, and chroma are present on pins 1, 2, & 3.  All 3 signals are independent copies of the same video and 1.0V P-P into 75 ohms.

All modes use 59.94 Hz rate for vertical sync.  VGA uses 31.469 KHz rate for horizontal sync, and all other modes use 15.734 KHz rate for horizontal sync.  The color subcarrier is 3.579545 KHz, giving NTSC operation.

Step By Step Building the Dazzler II Board
The build instructions are fairly simple for this board but because it is a complex board building it should not be rushed.  As always, first examine the bare board carefully for scratches or damaged traces, use a magnifying glass if need be.  A broken trace is almost impossible to detect by eye on a completed board.

Unlike most other boards on this site, this board has an extensive analogue signal component.  The values of the resistors are sometimes not common, but those values must be used. All resistors should be within 1% of the schematic quoted value.  All components are available from Mouser/DigiKey etc.

Build the board up in functional steps. Avoid the temptation of adding everything at once and popping it into your S-100 box. Step by step is faster in the end -- trust me.  We will set the board up configured as a self contained video board first independent of the S-100 bus.  In this mode we will program the U3 CPLD with a special test pattern to check its functionality.  Only when this works will we utilize the S100 bus section of the board.
Solder in all the required IC sockets, resistors, resistor arrays, capacitors, jumpers, and the 5V and -12 voltage regulators.  The -12V, LM7912 regulator does not need a heat sink but if you use a LM7805 be sure and add one.  The LM7912 however does need a mica insulator between itself and the board as well as a Teflon bolt. The back of the regulator should not be grounded. (The square pad where the bolt goes is actually not grounded,  but the is a danger of the nearby board front ground plane shorting through the varnish layer to the back or the regulator without the mica insulator).

Do not add the LED's yet. Be sure you put the resistor arrays in with the correct orientation of pin 1. Check their values before soldering (they are difficult to remove).  Insert all jumper arrays.
For prototype boards I generally use "double swipe" IC sockets. For a critical board like this I prefer to use "Machine Tooled" IC sockets.  However they are more expensive and you have to be particularly careful not to bend the IC pins.  The two clock oscillators can have their own special sockets (e.g. Jameco #133006) but actually I find the "Machine Tooled" IC sockets make a better connection.  I in fact solder the 2MHz oscillator directly to the board since it will never be changed.
Next insert all 3 LED's. Before soldering them in place bring to +5V  (D1, & D3)  or (-12V ,D2)  the appropriate pin to make sure it lights up.   I use a blue LED for D3 "Board Active".

Check the voltage to sockets on the board is about 5V by placing the board in your S-100 system using an extender board. With no load you will typically get 5.00V  (+/- 0.2V).  BTW, your system should boot and run correctly with its Z80 master CPU board. If not, you have a serious solder bridge somewhere on the board.  Before you do anything else with a magnifying glass go over every socket on the board and examine for a proper solder joints. I like to "reheat" each joint just to be on the safe side. The silk screen/varnish on these boards us quite thick. It's easy not to have a good solder joint for the ground pins.  Double check.   Extra time here will save you hours later, (Been there, done that! ). 

We will be utilizing the onboard RAM (U2) and CPLDs U3 and U1 to just generate a test pattern on the video output.  The only input being +8 and -16V's from the S100 bus.  
Insert the two board Oscillators, a 10 MHz oscillator in P1 and a 28.636 MHz oscillator in P9.
Next, we must program the CPLD's U3 and U1. Both are 1508's and are programed as we have done in the past for other S100Computers boards. See here.

Be sure you have the CPLD chips orientation correct. Pin 1 is the dot in the middle of the chips LHS edge as you read the label on the chip. 
For U3, pin 1 is at the center of the RHS of the chip in its socket.  
However for U1, the chip is rotated 90 degrees (to shorten critical connections to U6).   Pin 1 is in the middle top row of pins in the socket on the board.

The .JED file for U1 is DISPLAY_FINL4CS.JED
The test program .JED file for U3 is BJL_TESTGEN1_V5.JED

Both are available at the bottom of this page

The programmer connection for U3 is P2 or P3.  The programmer connection for U1 is P14 or P15.
Insert U3, U1 and the RAM chip U2.  Insert (only) U15, U16 & U17 and the two oscillators P1 & P9.
Carefully insert the following jumpers. K2 1-2 (for IEEE-696 16MB RAM addressing), K1 1-2 (for 16 bit Port addressing) and K4 1-2.
Jumper all top to bottom pins on P17.
Next we need to add jumpers to the large dual pin array P18. Pin 1 is on the top RHS, pin 40 is on the bottom LHS.

Jumper P18 as follows:-
40-39, 38-37,   34-33, 32-31, 30-29, 28-27, 26-25
All the rest of the pins are open.
Here is a close-up of the above jumpers. 
 Test Jumpers

Then program U1 (using the P14/P15 socket) and U3 (using the P2/P3 socket) with the two above .JED files.
Next insert the board into the S100 bus.  It should be configured exactly as seen in this picture:
 Test Board Setup
Here are two close-up pictures of the analogue sections of the board:-
It the top SW2 switch is to the right you should see the standard test pattern described above.
Setting it to the left causes the board to continuously display a moving pattern as shown in this short video.
The above moving test pattern should always run with the above test CPLD. 
If you see the above display you have programmed the CPLDs correctly and are well on your way to having a functional Dazzler II board.

We will now connect this board to the S100 bus/Z80 interface. 
First remove U3 and carefully store it. Remove all the jumpers on P17.
Program another 1508 CPLD with the .JED file for U3 is
BJL_VER4.JEDThis file can be downloaded from the bottom of this page.
Again, be sure you have the chip orientation correct. Pin 1 is the dot in the middle of the chips LHS edge.

Insert all the remaining 74LSxx IC's, EXCEPT U18.  Be careful to use the correct chip and have the pin one orientation correct. Double check.
Insert the 5 dip switches and set them as described above.

SW1  Unused here.
SW3  close,close,close,close,open,open,closed,closed.
SW5  All closed.
SW4  closed,closed,closed,closed,closed,open,open,open.
SW6  All closed.

Jumper P18 as follows:-
28-27, 30-29,   32-31, 34-33, and 4-3
All the rest of the pins are open.

Here is a close-up of the above jumpers. 

 Final Jumpers

You are now ready to fully utilize your Dazzler II.  The board is software compatible with most previous Cromemco TV Dazzler software (see below). However remember that many of those programs were written before the days of CPM and execute at 0H in RAM.  You will either need to reassemble them or after loading with CPM's SID,  manually move the program down to 0H in RAM.

To get started,  download the CPM modified KScope.exe supplied at the bottom of this page.  Here is a short video of this continuously running program.
Note this video will take time to upload/buffer when it is first run. Please wait.

The KSCOPE program itself can be obtained here
Other Dazzler games software can be found
below. There are also a few diagnostic programs. For example COLOR.COM is a CPM program that displays the range of colors available for programming. Here is a picture of the display patterns. Please note the actual colors/intensity do not copy well with my camera setup.
  Dazzler Color Range

The Dazzler II Board Joysticks
Terry Walker has written up a detailed Theory Of Operation for the board which can be seen here.

In summary however, s
ome of the original TV Dazzler games utilized two Joysticks for input.  The analogue input was provided a specialized board the Cromemco D+7A I/O board
.  This was a specialized board (quite unique in shape) and built before the days of the PC mouse or PlayStation etc. joysticks.  While not all will need or want this interface for this board,  the board has at its the top left hand corner input support for two Joysticks.  The interface is compatible with the Cromemco D+7A board. If there is sufficient demand we can have a small batch of boards done.   Here is a picture of a typical "box" and its internal circuit board.

The circuit is actually quite simple:-
Joystick Schematic

The BOM for this board is provided at the bottom of this page.  You will notice the board also contains a small speaker allowing one to send sound to the joystick box.

When the joystick board is build as shown above, it fits in the small Hammond 1590BB die cast box from DigiKey.  This design has the virtue that there is no wiring inside the box.  All connections are done by the PC board.  However, there are several problems with this design: 1) The pushbuttons shown are easily damaged by side forces, and alternatives have a small button which causes finger soreness with extended use. 2) The joystick, although inexpensive, small and easy to obtain, has some undesirable features in its mechanical 'feel' and electrical zero dead zone.  3) The miniature speaker is inefficient even when given 0.2 watt of audio power. 

The above problems can all be alleviated by using the circuit board as an interface tool and mounting it in a larger box, wired to better buttons and joystick, and a standard type 3 or 4 inch speaker.  The disadvantage is the additional cost of the improved components is substantial.

Adjustment of Joystick Pot
The Pot RV1 needs to be adjusted for the best joystick response.  To do so from your monitor,  read Port 19H and display the contents so you can see what is happening.  At the center, the joystick should return a code 000000000 +/- a few LSBs.  Adjust the Pot until you get close to this value. When you move the joystick to the far left, the code should be 10000000, and at the far right it should be 01111111.  You should be able to find intermediate locations for the joystick which give codes between these limits. 

Once you have the board up and running you can fine tune the joysticks with the ADCTEST.COM program.  It displays the X and Y values for both joysticks as you move them.  Here is a picture:-
  ADC Test

Dazzler II  Board Bugs/Notes
There is an important software consideration with this board which is not present in the original TV Dazzler.  This new design avoids the use of problematical DMA operation by having an on-board dual port SRAM for the memory which is actually displayed.  This memory can contain up to 4K bytes of information, and the TV Dazzler needs 2K bytes for the 64 by 64 color display.  In the original TV Dazzler, the DMA address in bits 6 to 0 of port 0EH is used to choose the starting point in main bus memory at which the image data will be read out.

In this new board, the SRAM is used to store a copy of the image data which is written to the main memory, and the DMA address of port 0EH is used to set the starting address of the 4K byte portion of main memory which will be copied by the SRAM.  Since the SRAM display memory will contain only what is written to the 2K of main memory that it overlays, it is imperative that the DMA address is set before the image data is written.  Otherwise the image will reside in main memory, but the SRAM will not have a copy of it.  So the image displays other random data instead.

This problem shows up in many of the original Dazzler games, where the initial image patterns were cleared or created before the TV Dazzler was turned on and the DMA address set.  With the new board, the initial screen seen on these games has random data in it instead.  Minor changes need to be made to the games to fix this problem. 

This problem was not found until the TV Dazzler games were located and run, after the board was fully debugged.  A future design could be done to fix this restriction, but it does require changing the CPLDs, adding an additional CPLD, and adding different SRAM chips to the board.  Surface mount components or a 4 layer board would probably be required as well.

The board has a few  non-standard TV Dazzler options that may be of interest.  The large jumper array P18 brings out a number of internal CPLD signals that were used for debugging/development. Most need not be used.   However P18 pins 33-34 and 35-36 allow you to define the type of video output the board will produce at the VGA connector J2.
Here are the video output mode options:-    
      P18 Jumpers:-  pin 35-36 pin 33-34
RGB Comp Video no jumper no jumper
Standard VGA no jumper jumper
Component Video jumper no jumper
Composite Video jumper jumper
These choices have no effect on the operation of any software.

The board has actually more onboard RAM than the original TV Dazzler could address.  Removing P18 jumper pins 31-32 switches the display page and moves the display area in the Z80's address space up 800H in RAM. If you insert U18, (a 74LS574), you can program its bit 0 to do this in software by outputting to the “Extra Port” (IC4, SW1).  Removing P18 jumper pins 3-4 changes the color lookup map to a second built in table in the U1 CPLD. Again if you insert U18, you can program its bit 1 to do in software.  In theory you could program another lookup table in the CPLD.

Note if you do use U18,  you must remove the P18 jumpers 3-4 and 31-32. This is important otherwise U18 will overheat since the gates on its pins 19 and 18 are grounded.

Dazzler Software.
Z80 Software for the Cromemco TV Dazzler was amongst the very first written for a "home computers".  Much of the software was written before CP/M was available and was distributed on paper tape or on a cassette tape.  Many of us can remember writing our first video programs for these "spectacular video boards",  the TV Dazzler (or the higher resolution but B/W, Solid State Music VDB-1 board).  In those days programs ran at 0H in RAM. You loaded the code there, hit reset and jumped to that location.   With the introduction of CPM, CDOS etc. the code had to be relocated to run at 100H in RAM. With source code this is trivial to do. However in some cases the source was lost or not available.  In such cases one has to build into the CPM code a small "code relocator" to shift the CPM file data down to 0H in RAM  and then jump to that location.  Of course CPM itself is no longer functional at that stage.  Depending on how much time you want to put into it,  that approach can be elaborated. 

I provide below (MOVE.Z80) as an example of a very simple approach. In CPM you join MOVE.COM with your Dazzler.COM file and save it with PIP to a CPM disk.  If your Dazzler file is a .HEX file you need to first convert it to a binary/.com file. I use the Wellon VP290 PROM burner software,  but the are many other ways. 

Here are some Dazzler programs that are provided with their source code and load at 100H in RAM and so should run with CPM.  Please note is some cases there is console I/O. There are two possibilities; Output directly to a hardware port or via CPM itself.  Modify the equate in the code as necessary.  With the direct hardware approach,  you don't have to have a functional CPM system to run the program.  You can use the MASTER.Z80 monitor to download the code (for example from a PC),  and directly run the program in S100 bus RAM at 100H.

As mentioned above there is very important difference in how this board differs from the original TV Dazzler.  The latter board set used DMA to access the Z80 RAM for video data.  Some Dazzler software switched the DMA pointer rather than move RAM bytes into a fixed location.  Programs for example, would use one DMA location for a menu/instructions and another for the actual graphics.  Fortunately this was not too common.  In many case if you clear the video RAM area before running the program the display is fine. For any of these Dazzler programs they can easily be adapted to this board if you have source code -- just a few LDIR Z80 instructions.  However in some cases the actual source code seems to be lost.  One has to resort to dis-assembling the .HEX or .COM file. 
Program Name Runs under CPM          Comments        Documentation 
KSCOPE CPM.ZIP Yes, with BDOS Print Signon Displays continuous color patterns on screen
KSCOPE_100H.zip No. Runs immediately at 100H in RAM, no signon etc. Use Monitor XModem command to load (XH,C).
ADCTEST.ZIP Runs under CPM Used to test Joystick circuit. Instructions are shown on CPM screen
SKETCH.ZIP Yes, with BDOS Signon Displays test pattern of lines on screen with joystick See source code
SOUND.ZIP Yes Joystick buttons emit different sounds Instructions on CPM screen
ADDRESS.ZIP Yes with BDOS signon Internal test of CPLD code. Draws "X" lines on screen Info is shown on CPM screen
X-Life.zip No. Runs immediately at 100H in RAM. Works best if screen is first   cleared. Use Monitor XModem command to load (XH,C).   Dazzler Games Manual
DOGFIGHT.ZIP Yes. Runs immediately at 100H in RAM. Works best if screen is first cleared. No signon etc.  Requires Joystick Inputs. Dazzler Games Manual
DAZCHESS.ZIP Yes. Runs immediately at 100H in RAM. Keyboard Input Microchess Manual
COLOR.ZIP Yes Shows range of colors available on Dazzler II Instructions are shown on CPM screen
SPACEWAR.ZIP Yes. Requires Joystick Inputs. No Source code, runs too fast with 10MHz Z80. Dazzler Games Manual
Dazzler Graphics Instruction Manual
Dazzler Games Manual
Dazzler Spacewar Manual
Cromemco Software Database
There is a large body of early software written for the TV Dazzler.   It is scattered all over the web.  Unfortunately most of it is in the form of .HEX or .BIN files with no source.  I have collected some of it and packaged it into the following DazzlerSoftwareCollection.zip file.  Please feel free to browse/edit/debug any program. If you can hammer one into shape so it signs on and later off in CPM please forward it to me so I can post it above for others to share.  Writing/altering these programs is a very rewarding experience. A few hundred bytes of Z80 code can often yield spectacular results. 

My hope is we will eventually have here a table of bug free, CPM running Dazzler programs with the corresponding documentation. Credit will be posted in the comments section for the "authors".
A Production S-100 Board.
Realizing that a number of people might want to utilize a board like this together with a group of people on the  Google Groups S100Computers Forum, "group purchases" are made from time to time.  Please see here for more information.
The links below will contain the most recent schematics of these boards.
Note, it may change over time and some IC part or pin numbers may not correlate exactly with the text in the article above.
Also the CPLD codes may change from what is in the text above. Use the most recent CPLD codes provided below.

Dazzler II Schematic
                    (V2.1d     9/1/2016)
Dazzler II Board Layout
              (V2.1d     9/1/2016)
Dazzler II  KiCAD Files                  (V2.1d     9/1/2016)
Dazzler II  CPLD Files                    (V2.1d     10/3/2016)
Dazzler II Gerber  Files                  (V2.1d     9/1/2016)
(V1.0     9/17/2016)
Dazzler II BOM
                                 (10/11/2016    Supplied by Rick Bromagem)
Joystick Board Gerber Files
                (V1.0    10/14/2016)
Joystick Board BOM                        (V2.1d     10/10/2016)

Other pages describing my S-100 hardware and software.
Please click here to continue.

This page was last modified on 02/17/2019