S100 Computers - RAM + PROM Board II

A 1MG or 16 MG RAM + EEPROM S-100 Memory Board

Introduction
Our original EPROM S-100 board and RAM+ROM Boards proved very popular. All production quality boards were quickly taken. A number of people have requested an "All in One" RAM/ROM combination board capable of working in 8 or 16 bit S-100 systems with pre or post IEEE-696 CPU boards and capable of accepting up to 16 MB of RAM. Also in view of the range of chips and CPU's a flexible wait state circuit that can independently assign 0-8 wait states to the above ROM chips would be desirable. It would also be nice if the EPROM could be phantom/shadowed in or out depending on which CPU is controlling the S-100 bus. For example one normally would not want a Z80 monitor at F000H if the bus has given control to an 8086 in a 1 or 16 MG address space but you would like a ROM at FFFFFH.

In an attempt to address these needs I present the above board. It should meet the above requirements, the only catch is that in order to do this one has to very carefully configure the board for the diverse range of memory chips it can accommodate.   This requires a careful analysis of each memory chips I/O pins, matching the boards jumpers accordingly. Also one has to match switches and jumpers with the desired range of address you wish the RAM chips to reside in for the S-100 buss's address space. This can be a little challenging. To get people started I will provide a small sample of possible combinations.

A common example will be illustrated that is configured to contain:-
    An 8 bit 28C64 4K EEPROM at C000H (for say a Z80 Floppy Disk Controller BIOS).
    One Meg of Static RAM from 0H to FFFFFH (for the 8 bit Z80, and a 16 bit 8086 CPU).
    Zero to 8 wait states can be added to the EEPROM if needed.
    The 8 bit EEPROM can be inactivated if the 8086 is controlling the bus. It reappears if control is passed back to the Z80.

Another example will be illustrated that is configured to contain:-
    An 8 bit 28C010 128K EEPROM at FF000H (for say an 80486 Monitor).
    16 MG of Static RAM from 0H to FFFFFFH (for a 16 bit 80486 CPU).
    Zero to 8 wait states can be added to the EEPROM if needed.

S-100 Bus 8 & 16 Bit Data Paths
If you are using any of our previous RAM boards by now you probably know how 8 and 16 bit data paths are handled on the S100 bus. If not, please see the discussion for the 4MG RAM Board. In summary 8 and 16 bit data is handled differently on the S100 bus. Eight bit data has separate 8 bit data in and data out paths on the bus. For 16 bit data both these paths (16 S100 bus lines) are rearranged into a single 16 bit bidirectional data bus. The current S100 bus master CPU sends out a signal indicating each time if the data on the bus is going to be 8 or 16 bit data. The receiving bus board must rearrange its bus drivers accordingly for each and every data byte/word sent.

The RAM Circuit
I wanted to build a S-100 RAM/ROM board that would serve me well into the future. Where I could use it with very fast and bit wide CPU's. Where possible I wanted to stick with DIP type chips. There are higher density RAM chips than the 512K/chips we use here, but many are SMD chips. I have had good success with the 32 Pin DIP Alliance AS6C4008 (512KX8 Static RAM) chips, (Jameco Part #1927617) with the 4MG Static RAM Board. I wanted to be able to use this chip again here. However two chips will only get 1 MB of RAM. To get the S100 bus maximum RAM capacity we need 16MB. In the past we used 4X4MB SMD chips on an 2X20 pin mini adaptor board. These have the advantage that you only have to solder them once and can move them from board to board. See 16MB RAM Boards. Today there are 8MB SMD RAM chips (AS6C6416's), so two of these would completely fill your S100 bus.

The circuit itself for 8 and 16 bit data transfers has been discussed previously for our 4MB and 16MB RAM boards. Here is the core circuit.

You will notice I have gone back to a non-GAL chip circuit. Not only does this avoid the need for a GAL programmer but much to my surprise I have found this (somewhat convoluted) circuit gave the most reliable RAM boards with a wide range of high speed CPUs we have done over the years. Note the use of 74Fxx chips.

The board can utilize a number of Static RAM chips:-
Alliance AS6C4008 512K X8 RAM.    (Two), for 1MB of RAM always 0-0FFFFFH. Vcc always 5.0 Volts.
Cypress CY62167E 2MB X8 RAM.     (Two) 2X20 pin SMD mini adaptors always 0-3FFFFFH, 4 chips/Adaptor. Vcc always 5.0 Volts
Cypress CY6216DV30 2MB X8 RAM.  (Two) 2X20 pin SMD mini adaptors always 0-3FFFFFH, 4 chips/Adaptor. Vcc always 3.4 Volts
Alliance AS6C3216 4MB X8 RAM.      (Two) 2X20 pin SMD mini adaptors always 0-3FFFFFH, 2 chips/Adaptor. Vcc always 3.4 Volts
Alliance AS6C6416 8MB X8 RAM.     (Two) 2X20 pin SMD mini adaptors* always 0-3FFFFFH, 1 chips/Adaptor. Vcc always 3.4 Volts

Note it is absolutely essential that the Vcc voltage supply to these RAM chips is correct. Be absolutely sure you have the jumper K3 set correctly for the SMD RAM chips (The AS6C40078 512K RAMs are always 5V).

The address range for the RAM chips is simple. The first 1MB of RAM for the AS6C4008 chips. All available RAM (16 MB) for the SMD chips. There are no RAM start address jumpers. Note the S100 bus Phantom line (pin 67), if low will inactivate all RAM on the board. This is typically used to place an EPROM in the address space and is used here with the onboard ROM if activated (see below). Finally, note you cannot have the 1MB RAM chips on the board as well as the 16MB RAMs. You need to pull one or the other.

The AS6C4008 chips utilize all the address lines going to them - always. However the 2MB, 4MB and 8MB SMD RAM chips need to have the jumpers K2 ,K3, K4 and K5 set correctly to function properly (see below).

Unfortunately the old V06d SMD mini adaptors will not work with the new AS6C6416 8MB chips. Those adaptors do not bring in the address line A23. A slightly modified SMD mini adaptor (V7.0) is required (see below).

The ROM Circuit
The board can be used with two different size EEPROMS. You can use a 28C64 8K EEPROM or a 27C010 128K EEPROM, (or similar UV PROMS).

For the 8K EEPROM you need to insert the DIP chip in the right-most socket pins as shown here:-


	28C64		27C010

Next we have a circuit to hide or expose the EEPROM on the S100 bus. There are two options. Either the ROM is visible to the bus master CPU upon power up and can be inactivated/invisible by outputting to a defined IO port, or vica versa, it is invisible until a byte (any byte value) is output to a define port.

Any 8 bit port can be used. I use 1DH, a port not currently used on any other of my boards. LED D6 indicates if the onboard EEPROM is active or not. It must be configured to do so with jumper K1. Jumper JP4 determines if the EEPROM is active or not on power up.
Here is a summary.


	PROM Inactive on power up/reset Activeted with Port output	PROM Active on power up/reset Inactivated with Port output
	JP4 Opened, K1 2-3	JP4 Closed, K1 1-2

Finally there is a circuit to add wait states to the current bus master CPU when the EEPROM is active.
We use the following tried and true circuit:-

The number of wait states required is set with SW1. If you do add wait ststes you must also close Jumper P8 (S100 RDY).
Because the EEPROM CS* is always active on this board, few if any wait states are needed with most CPUs and newer EEPROMS.
The fast RAM chips on this board never require CPU wait states.

Step By Step Building The Board.
The first step is to examine the board carefully for scratches or damaged traces. Use a magnifying glass if need be. The quality of the boards we get from PCB Cart is excellent. I must have done over 100 boards by now, never had a problem, but there is always a first time. A broken trace is almost impossible to detect by eye on a completed board.

Next solder in all the required IC sockets, resistor arrays, capacitors, jumpers, and the switches SW1, SW2 and SW3. Be sure you put the resistor arrays in with the correct orientation of pin 1. Check their values before soldering (they are difficult to remove).

Note there are two sockets for the Pololu 5V and 3.3V regulators. While the older ones (D24V25F5 and D24V25F3) are still available and use P5 and P7, it seems Pololu is suggesting users use the newer D24V22F5's (5V, 2.5 Amp) units. It has a different pinout, use this one in P4. More recently they also added the equivalent D24V22F3 3.3V regulators. It also has a different pinout, use this one in P7. Be sure you get these regulators/ correct. To be safe once inserted, check the voltage in your system on a 5V and 3.3V IC, (see the schematic) with no chips yet inserted on the board. 5V and 3.3V going to the correct pins of the FPGA adaptor. (5V going to the 3.3V pins will blow the unit!). Please note Pololu has come out with more 5V and 3.3v regulators. Please examine the pinouts and match them with the board sockets. Unfortunately the newer 5V and 3.3V units look exactly the same on the surface. Presumably some of the internal resistors are different to give 5V and 3.3V.

While not really recomemded, you can use the old 5V (LM7805) and 3.4V (LM3940) linear voltage regulators. The 5V one will require a heat sink.
Alternatively you can use EzSBC regulators.

For prototype boards I generally use "double swipe" IC sockets. For a critical board like this I prefer to use "Machine Tooled" IC sockets. However they are more expensive and you have to be particularly careful not to bend the IC pins.

Check the voltage to sockets on the board is about 5V by placing the board in your S-100 system using an extender board. With no load you will typically get between 4.9 and 5.1 Volts. BTW, your system should boot and run correctly with its Z80 CPU. If not, you have a serious solder bridge somewhere on the board. Before you do anything else with a magnifying glass go over every socket on the board and examine for a proper solder joint. I like to "reheat" each joint just to be on the safe side. The silk screen/varnish on these boards us quite thick. It's easy not to have a good solder joint for the ground pins. Double check.   Extra time here will save you hours later!

The 1MB RAM Section
This board consists of 3 sections. A 1MB RAM section, a 16MB RAM section and an 8 bit wide EEPROM section.
We will build and test the board one section at a time. First the 1 MB RAM section.

Add all IC's to the board including the 512K RAM chips U11 and U26.
Only install the jumper JP8.

Install the board in the S100 bus with just a Z80/8080 CPU board with its own ROM monitor and some kind of S100 bus Console IO board.
Typically this would be our Z80 CPU board and Console IO Board. If you don't have a CPU board with it's own onboard ROM boot monitor you need to go directly to the ROM section below.
With the Master "A" command you should see the following memory map.

The complete memory map must be "R's" except for the CPU ROM area -- usually F000H-FFFFH. If you see a "P" or "." there is a problem with the address or data chips on the board. First check for a bad solder joint of bent IC pin. During the memory map display the 8 bit read and write LEDs D2 and D3 should flash. The D5 and D4 should not.

If your system will not boot with this RAM board you probably have a RAM access problem. The easiest way to debug such a system is to remove U19 so the board does not write data to the S100 bus and add another known working RAM board - like an old 4K RAM board. Hand enter code to read a RAM location in a tight loop and follow the board circuits with a logic probe. Likewise do the same write to a RAM location.

The EEROM Section
With the 1MB RAM section working next we will install an 8 bit 28C64 EEPROM. Set the jumpers JP4 Open, and K1 2-3
Set the EEPROM activation port to 1DH.

Install the programmed EEPROM (a 28C64) in the right-most position of the P12 32 pin DIP socket. You can program the PROM with anything you like and position it anywhere in the 16MB Address space.
For testing we will start with 00000H-7FFFH.
Set the jumpers as follows:-

P1	Size	Address	Type	K8	K9	K10	K11	P9,P10	P11	SW2
28C64	32K	0000H-7FFFH	EEPROM	1-2	1-2	1-2	1-2	P10,1-2 P10,3-4 P10,5-6 P10,7-8 P10,10-P9,5	P11,1-2 P12,3-4 P13,5-6 P14,7-8 P14,9-10	All Closed
28C64	2K	0000H-07FFH	EEPROM	2-3	2-3	2-3	2-3	P10,1-P9,1 P10,3-P9,2 P10,5-P9,3 P10,7-P9,4 P10,10-P9,5	P11,1-2 P12,3-4 P13,5-6 P14,7-8 P14,9-10	All Close
28C64	2K	8000H-87FFH	EEPROM	2-3	2-3	2-3	2-3	P10,1-P9,1 P10,3-P9,2 P10,5-P9,3 P10,7-P9,4 P10,10-P9,5	P12,3-4 P13,5-6 P14,7-8 P14,9-10	All Closed
28C64	2K	E000H-E7FFH	EEPROM	2-3	2-3	2-3	2-3	P10,1-P9,1 P10,3-P9,2 P10,5-P9,3 P10,7-P9,4 P10,10-P9,5	P14,7-8 P14,9-10	All Closed
28C64	4K	C000H-CFFFH	EEPROM	2-3	2-3	2-3	2-3	P10,1-P9,1 P10,3-4 P10,5-6 P10,7-8 P10,9-10	P11,1-2 P12,3-4 P13,5-6	All Closed
28C64	4K	E000-EFFFH	EEPROM	2-3	2-3	2-3	2-3	P10,1-P9,1 P10,3-4 P10,5-6 P10,7-8 P10,9-10	P11,1-2 P12,3-4	All Closed


	0000H-7FFFH		0000H-07FFH		8000H-87FFH		E000H-E7FF

Because of the ROM configuration flexibility the above jumpers are a little difficult to figure out. Please study the schematic carefully. I find its actually quicker to move a few jumpers around and then do a Memory Map, see what you get and try again.
One complication with setting the range E000H-EFFFH (Below the CPU ROM monitor stack F000H-FFFFH), you cannot use the Master monitor QO 1D,FF command to activate the ROM because you have now overwritten the stack. You can have the board ROM active (at E000H-EFFFH) on Power On or Rreset using the JP4 + K1. Alternatively after a monitor ROM activation routine reset the stack.

Normally you would use the 28C64 EEPROM for a Z80/8080 Monitor and the 27C010 EEPROM for a 16 bit CPU . Normally the 28C64 will reside in the lowest 64K of the S100 bus 16MB address space while the 27C010 will reside at the top 1 or 16 MB position. You can fine tune the EEPROM address and address range using the dip switch SW3 and jumpers P9+P10 & P11 (see below).

P1	Size	Address	Type	K8	K9	K10	K11	P9,P10	P11	SW2
27C010	64K	C0000H-CFFFFH	EEPROM	2-3	2-3	2-3	2-3	P10,1-P9,1 P10,3-P9,2 P10,5-P9,3 P10,7-P9,4 P10,10-P9,5	P11,1-2 P12,3-4 P13,5-6 P14,7-8 P14,9-10	Close Close Close Close Open Open Close Close
27C010	8K	C0000H-C1FFFH	EEPROM	2-3	2-3	2-3	2-3	P10,1-P9,1 P10,3-4 P10,5-6 P10,7-8 P10,9-10	P11,1-2 P12,3-4 P13,5-6 P14,7-8 P14,9-10	Close Close Close Close Open Open Close Close

Normally for 16 bit systems you do not want the Z80 ROM visible in the lower 64K address space. With onboard ROM CPU boards this is usually not a problem since the ROM is inactivated when the 8 bit CPU releases control to the 16 bit CPU. Howeve if you are using the ROM on this board with the 8 bit CPU you normally would inactivate it in the 16 bit ROM monitor/BIOS.

The 16 MB RAM Section
We now come to the main function of the board adding 16MB of static RAM. We use two 8 MB 2X20 pin Mezzanine mini boards used on out earlier 16 MB RAM boards. However we have the option of a few RAM chips types/capacities. This applies to their address lines A21, A22 and A23.

Remove the two RAM chips in U11 and U26.
If possible borrow two working Mezzanine mini boards from a working 16 MB RAM boards. Otherewise solder 2 or 4 the SMD RAM chips to the mezzanine mini-boards (see below)

You need to carefully setup the RAM chip jumpers:-
Table

tly sure you have the RAM chip voltage set correctly with jumper K2. If in fact you never intend to change the RAM chip type you might conside soldering in a small wire jumper.
A good test is to insert the IDE/CF card board in the bus and boot CPM3.
Another test is to insert an 8086, 80286 or 80486 CPU slave board and do a Memory Map with those CPU's.

Source of Chips
Most of the chips on this board are quite common. A good source of 74LSxx and 74Fxx chips is Jameco, Mouser or DigiKey.
The 512K Static RAMs can be obtained from Jameco, #1927617. 28C64's the same, #39714.

To Order a Production S-100 Board
A number of people may want to utilize a board like this. Together with a group of people on the Google Groups S100Computers Forum, a "group purchases" was setup. This group purchase is now closed. Also a few long term users maintain a stock of some of our most popular boards. They are listed here (along with a number of other "ReteroBrew Computer" boards).

Please see here:-
https://www.retrobrewcomputers.org/doku.php?id=board inventory for a list of boards available.

MOST CURRENT EPROM BOARD SCHEMATIC (V1.3 6/7/2025)
Most current KiCAD files for this board (V1.0 4/18/2014)

Gerber files or this board (V 1.3 6/7/2027)

Other pages describing my S-100 hardware and software.
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