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A 1MG  or 16 MG RAM + EEPROM S-100 Memory Board

  RAM+ROM Board II

Our original EPROM S-100  board and RAM+ROM Boards proved very popular. All production quality boards were quickly taken.  A number of people have requested an "All in One" RAM/ROM combination board capable of working in 8 or 16 bit S-100 systems with pre or post IEEE-696 CPU boards and capable of accepting up to 16 MB of RAM.  Also in view of the range of chips and CPU's a flexible wait state circuit that can independently assign 0-8 wait states to the above ROM chips would be desirable.  It would also be nice if the EPROM could be phantom/shadowed in or out  depending on which CPU is controlling the S-100 bus.  For example one normally would not want a Z80 monitor at F000H if the bus has given control to an 8086 in a 1 or 16 MG address space but you would like a ROM at FFFFFH.

In an attempt to address these needs I present the above board.  It should meet the above requirements, the only catch is that in order to do this one has to very carefully configure the board for the diverse range of memory chips it can accommodate.   This requires a careful analysis of each memory chips I/O pins, matching the boards jumpers accordingly.  Also one has to match switches and jumpers with the desired range of address you wish the RAM chips to reside in for the S-100 buss's address space.  This can be a little challenging.  To get people started I will provide a small sample of possible combinations. 

A common example will be illustrated that is configured to contain:-
    An 8 bit 28C64 4K EEPROM at C000H (for say a Z80 Floppy Disk Controller BIOS).
    One Meg of Static RAM from 0H to FFFFFH (for the 8 bit Z80, and a 16 bit 8086 CPU).
    Zero to 8 wait states can be added to the EEPROM if needed.
    The 8 bit EEPROM can be inactivated if the 8086 is controlling the bus. It reappears if control is passed back to the Z80.

Another example will be illustrated that is configured to contain:-
    An 8 bit 28C010 128K EEPROM at FF000H (for say an 80486 Monitor).
    16 MG of Static RAM from 0H to FFFFFFH (for a 16 bit 80486 CPU).
    Zero to 8 wait states can be added to the EEPROM if needed.

S-100 Bus 8 & 16 Bit Data Paths
If you are using this board by now you probably know how 8 and 16 bit data paths are handled on the S100 bus. If not, please see the discussion for the 4MG RAM Board. In summary 8 and 16 bit data is handled differently on the S100 bus.  Eight bit data has separate 8 bit data in and data out paths on the bus.  For 16 bit data both these paths (16 S100 bus lines) are rearranged into a single 16 bit bidirectional data bus.  The current S100 bus master CPU sends out a signal indicating each time if the data on the bus is going to be 8 or 16 bit data.  The receiving bus board must rearrange its bus drivers accordingly for each and every data byte/word sent.

The RAM Circuit
I wanted to build a S-100 RAM/ROM board that would serve me well into the future. Where I could use it with very fast and bit wide CPU's. Where possible I wanted to stick with DIP type chips. There are higher density RAM chips than the 512K/chips we use here,  but many are  SMD chips. I have had good success with the 32 Pin DIP Alliance AS6C4008 (512KX8 Static RAM) chips, (Jameco Part #1927617) with the 4MG Static RAM Board. I wanted to be able to use this chip again here. However two chips will only get 1 MB of RAM.  To get the S100 bus maximum RAM capacity we need 16MB.  In the past we used 4X4MB SMD chips on an 2X20 pin mini adaptor board.  These have the advantage that you only have to solder them once and can move them from board to board. See 16MB RAM Boards. Today there are 8MB SMD RAM chips (AS6C6416's), so two of these would completely fill your S100 bus.  On top of the there are nice 48 pin TSOP to 48 pin DIP adaptors that allow you to move chips from board to board. We only need two RAM chips for this 16 MB RAM Board!  What a contrast to the RAM chip requirements for early S100 bus RAM boards!

The circuit itself for 8 and 16 bit data transfers has been discussed previously for our 4MB  and 16MB RAM boards. Here is the core circuit.
    Circuit 1
You will notice I have gone back to a non-GAL chip circuit. Not only does this avoid the need for a GAL programmer but much to my surprise I have found this (somewhat convoluted) circuit gave the most reliable RAM boards with a wide range of high speed CPUs we have done over the years. Note the use of 74Fxx chips.

The board can utilize a number of Static RAM chips:-
Alliance AS6C4008  512K X8 RAM.    (Two), for 1MB of RAM always 0-0FFFFFH. Vcc always 5.0 Volts.
Cypress CY62167E  2MB X8 RAM.     (Two) on 2X20 pin SMD mini adaptors always 0-3FFFFFH,  4 chips/Adaptor. Vcc always 5.0 Volts
Cypress CY6216DV30 2MB X8 RAM.  (Two) on 2X20 pin SMD mini adaptors always 0-3FFFFFH,  4 chips/Adaptor. Vcc always 3.4 Volts
Alliance AS6C3216 4MB X8 RAM.      (Two) on 2X20 pin SMD mini adaptors always 0-3FFFFFH,  2 chips/Adaptor. Vcc always 3.4 Volts
Alliance AS6C6416  8MB X8 RAM.     (Two) 48 pin TSOP chips directly soldered to the board.  Vcc always 3.4 Volts

Note it  is absolutely essential that the Vcc voltage supply to these RAM chips is correct.  Be absolutely sure you have the jumper K3 set correctly for the SMD RAM chips (The AS6C4008 RAMs are always 5V).
    Voltage Jumper
The address range for the RAM chips is simple.  The first 1MB of RAM for the AS6C4008 chips. All available RAM (16 MB)  for the SMD chips. There are no RAM start address jumpers. Note the S100 bus Phantom line (pin 67), if low will inactivate all RAM on the board. This is typically used to place an EPROM in the address space and is used here with the onboard ROM if activated (see below).  Finally, note you cannot have the 1MB RAM chips on the board as well as the 16MB RAMs. You need to pull one or the other. However you can inactive the two AS6C6416's soldered directly to the board by jumpering K7 1-2 (ground).

The AS6C4008 chips utilize all the address lines going to them - always.  However the 2MB, 4MB and 8MB SMD RAM chips need to have the  jumpers
K2 ,K3, K4 and K5 set correctly to function properly.
RAM Chip K2 K3 K4 K5 K6
CY62167E 2-3 2-3 1-2 1-2 1-2
CY6216DV30 1-2 2-3 1-2 1-2 1-2
AS6C3216 1-2 2-3 1-2 2-3 1-2
AS6C6416 1-2 1-2 2-3 2-3 1-2
AS6C6416* 1-2 1-2 2-3 2-3 2-3
AS6C6416* utilizes a modified version of our 2X20 Pin Mezzanine RAM mini boards (V7.0), where its pin 2 delivers the address line A22 (instead or Vcc).
If you wish to use this two chips you cannot use the "old V06c" of our previous mezzanine boards. You will need the newer V7.0 mezzanine boards. The V7.0 of course will also work with the earlier boards/chips.  Alternatively you can simply solder the 48 pin TSOP chip directly to the board.

The ROM Circuit
The board can be used with two different size EEPROMS. You can use a 28C64 8K EEPROM or a 27C010 128K EEPROM, (or similar UV PROMS).  BTW, other UV and EEPROMS can be used you just need to match up the jumpers.
   ROM Circuit
For the 8K EEPROM you need to insert the DIP chip in the right-most socket pins as shown here:-
   28C64   29EE010 EEPROM
                                   28C64                                   27C010
Next we have a circuit to hide or expose the EEPROM on the S100 bus.  There are two options. Either the ROM is visible to the bus master CPU upon power up and can be inactivated/invisible by outputting to a defined IO port, or vice versa, it is invisible until a byte (any byte value) is output to a define port.
   ROM Port Circuit
Any 8 bit port can be used. I use
1DH, a port not currently used on any other of my boards. LED D6 indicates if the onboard EEPROM is active or not. It must be configured to do so with jumper K1.  Jumper JP4 determines if the EEPROM is active or not on power up.
Here is a summary.
  No ROM on Reset ROM on Reset
    PROM Inactive on power up/reset
Activated with Port output
PROM Active on power up/reset
Inactivated with Port output
  JP4 Opened,  K1 2-3 JP4 Closed,  K1 1-2

Finally there is a circuit to add wait states to the current bus master CPU when the EEPROM is active. 
We use the following tried and true circuit:-
  ROM Wait states circuit
The number of wait states required is set with SW1. If you do add wait states you must also close Jumper P8 (
S100 RDY).
Because the EEPROM is always active on this board, few if any wait states are needed with most CPUs and newer EEPROMS.
The fast RAM chips on this board never require CPU wait states.

Step By Step Building The Board.
The first step is to examine the board carefully for scratches or damaged traces. Use a magnifying glass if need be. The quality of the boards we get is excellent. I must have done over 100 boards by now, never had a problem, but there is always a first time. A broken trace is almost impossible to detect by eye on a completed board.

Next solder in all the required IC sockets, resistor arrays, capacitors, jumpers, and the switches SW1, SW2 and SW3. Be sure you put the resistor arrays in with the correct orientation of pin 1.  Check their values before  soldering (they are difficult to remove). 

Note there are two sockets for the Pololu 5V and 3.3V regulators. While the older ones (D24V25F5 and D24V25F3) are still available and use P3 and P4, it seems Pololu is suggesting users use the newer D24V22F5's (5V, 2.5 Amp) units, it has a different pinout, use this one in P2 (not P3).  More recently they also added the equivalent D24V22F3 3.3V regulators. Unfortunately in their wisdom they again changed the pinout connections. You must use the Pololu D24V25F3 3.3 V regulator in P4 or the D24V22F3 regulator in P21.   Be sure you get these regulators/ correct. To be safe once inserted, check the voltage in your system on a 5V and 3.3V IC, (see the schematic) with no chips yet inserted on the board. 5V and 3.3V going to the correct pins of the FPGA adaptor.  (5V going to the 3.3V pins will blow the unit!).  Please note Pololu has come out with more 5V and 3.3v regulators.  Please examine the pinouts and match them with the board sockets.  Unfortunately the newer 5V and 3.3V units look exactly the same on the surface. Presumably some of the internal resistors are different to give 5V and 3.3V.
While not really recommended, you can use the old 5V (LM7805) and 3.4V (LM3940) linear voltage regulators. The 5V one will require a heat sink.

For prototype boards I generally use "double swipe" IC sockets. For a critical board like this I prefer to use "Machine Tooled" IC sockets.  However they are more expensive and you have to be particularly careful not to bend the IC pins. 

Check the voltage to sockets on the board is about 5V by placing the board in your S-100 system using an extender board. With no load you will typically get between 4.9 and 5.1 Volts.  BTW, your system should boot and run correctly with its Z80 CPU. If not, you have a serious solder bridge somewhere on the board.  Before you do anything else with a magnifying glass go over every socket on the board and examine for a proper solder joint. I like to "reheat" each joint just to be on the safe side. The silk screen/varnish on these boards us quite thick. It's easy not to have a good solder joint for the ground pins.  Double check.   Extra time here will save you hours later!

The 1MB RAM Section

This board consists of 3 sections. A 1MB RAM section, a 16MB RAM section and an 8 bit wide EEPROM section. 
We will build and test the board one section at a time. First the 1 MB RAM section. 

Add the following IC's to the board:
Also add the 512K RAM chips U11 and U26.

Only install the jumpers JP8.
For now set all 3 Dip Switch arrays (SW1, SW2 & SW3) OFF.
      1MB RAM Board
Install the board in the S100 bus with just a Z80/8080 CPU board with its own ROM monitor and some kind of S100 bus Console IO board.
Typically this would be our Z80 CPU board and Console IO Board. If you don't have a CPU board with it's own onboard ROM boot monitor you need to go directly to the ROM section below.
With the Master "A" command you should see the following memory map.
   64K mem map
The complete memory map must be "R's" except for the CPU ROM area -- usually F000H-FFFFH. 
If you see a "P" or "." there is a problem with the address or data chips on the board. First check for a bad solder joint of bent IC pin. 
During the memory map display the 8 bit read and write LEDs D2 and D3 should flash.  The D5 and D4 should not.

If your system will not boot with this RAM board you probably have a RAM access problem.
The easiest way to debug such a system is to remove U19 so the board does not write data to the S100 bus and add another known working RAM board - like an old 4K RAM board.
Hand enter code to read a RAM location in a tight loop and follow the board circuits with a logic probe. Likewise do the same write to a RAM location.

The EEROM Section
With the 1MB RAM section working next we will install an 8 bit 28C64 EEPROM. Set the jumpers
JP4 Open (ROM Active), and K1 2-3 (ROM LED).
We will use a EEPROM activation port of
So set SW2 to (
1DH):- Close, Close, Close, Open, Open, Open,Close, Open. (Switches left tp right).
Set SW3 to all closed/on. With this setting IC1 pin 19 should be low.
Add IC1, IC2, IC3, U33 & U34.
Install the programmed EEPROM (a
28C64) in the right-most position of the P12 32 pin DIP socket. You can program the PROM with anything you like and position it anywhere in the 16MB Address space.
You need to carefully study the ROM selection circuit to figure out the jumper arrangement.
Remember Pin 19 of a 74LS682 will go low whenever the polarity of its pins 2,4,6,11,13,15 & 17 exactly match the polarity of its pins 3,5,7,12,14,16 & 18.
You can check the polarity of its pins 3,5,7,12,14,16 & 18  with a logic probe.
Here are a few examples:- 
P1 Size Address Type K8 K9 K10 K11 P9,P10 P11 SW3
28C64 4K 0000H-0FFFH EEPROM 1-2 1-2 1-2 1-2 A15,close

28C64 2K 0000H-03FFH EEPROM 1-2  1-2 1-2 1-2 A15,close

28C64 2K 8000H-87FFH EEPROM 1-2 1-2 1-2 1-2 A15,close


28C64 2K E000H-E7FFH EEPROM 1-2 1-2 1-2 1-2 A15,close


28C64 8K C000H-DFFFH EEPROM 1-2 1-2 1-2 1-2 A15,close

28C64 2K D000-D7FFH EEPROM 1-2 1-2 1-2 1-2 A15,close


ROM at 0H
  0000H-0FFFH   0000H-07FFH   8000H-87FFH   E000H-E7FFH

Because of the ROM configuration flexibility the above jumpers are a little difficult to figure out. I find its actually quicker to move a few jumpers around and then do a Memory Map, see what you get and try again.
One complication with setting the range E000H-EFFFH (Below the CPU ROM monitor stack F000H-FFFFH), you cannot use the Master monitor
QO 1D,FF Command to activate the ROM because you have now overwritten the stack.  You can have the board ROM active (at E000H-EFFFH) on Power On or Reset using the JP4 + K1. Alternatively after a monitor ROM activation routine reset the stack. 

Normally you would use the 28C64 EEPROM for a Z80/8080 Monitor and the 27C010 EEPROM for a 16 bit CPU .  Normally the 28C64 will reside in the lowest 64K of the S100 bus 16MB address space while the 27C010 will reside at the top 1 or 16 MB position.  You can fine tune the EEPROM address and address range using the dip switch SW3 and jumpers P9+P10 & P11 (see below).
P1 Size Address Type K8 K9 K10 K11 P9,P10 P11 SW3
27C010 32K C0000H-C1FFFH EEPROM 1-2 2-3 1-2 1-2 A15,close
27C010 512K E0000H-EFFFFH EEPROM 2-3  2-3 2-3 2-3 A15,P9,5
Normally for 16 bit systems you do not want the Z80 ROM visible in the lower 64K address space. With onboard ROM CPU boards this is usually not a problem since the ROM is inactivated when the 8 bit CPU releases control to the 16 bit CPU. However if you are using the ROM on this board with the 8 bit CPU you normally would inactivate it in the 16 bit ROM monitor/BIOS on for example the MSDOS Support Board. 
Also in some cases depending upon how much of the actual ROM you will be using (or the type or ROM),  you need to configure K8, K9, K10, and K11. Please see the schematic.

The only thing I have not added to this board is the "trick" I used on the Z80 CPU board where on can select the "upper" or "lower" 2K of ROM in a 4K ROM by outputting a bit to a defined port. 
If you absolutely need this you could write a routine to copy one of the 2K ROM blocks to RAM "underneath the ROM" and then inactive the ROM (i.e. flip back and forth RAM/ROM).

The EEROM Wait States Section
With the ROM  section working next we will install a circuit that allows you to install wait states for ROM reads with older CPU's. 
There is really no need for S100 bus RAM wait states with the chips we us on this board.
Install U27 and U29.  Install the
P8 jumper (S100 bus RDY).
Go back to using a 28C64 EEPROM and 4K of ROM starting at 0H as described above.  Be sure all switches on
SW3 are closes (i.e.. A23-A16 = 0).
Activate the EEPROM port of 1DH. Set 1 ,2,3... or 7 ROM read wait states with SW1.  Displaying RAM
from 0 to 1000H should activate the LED D10 indicating memory read wait states are being inserted on the bus.  Note because the EEROM CS* is active all the time most modern day EEPROMs will not require wait states.

The 16 MB RAM Section

We now come to the main function of the board adding 16MB of static RAM.  We have two RAM chip option arrangements.
1. Two 8 MB 2X20 pin Mezzanine mini boards used on out earlier 16 MB RAM boards
2. Two 8 MB 48 pin TSOP SMD
AS6C6416 chips soldered directly to the board.

Add U4, a 74LS139.

Lets us first go with option number 1. Remove the two RAM chips in U11 and U26.
If possible borrow two working Mezzanine mini boards from a working 16 MB RAM board.  Otherwise solder 2 or 4 the SMD RAM chips to the V06c mezzanine mini-boards (see below)

You need to carefully setup the  RAM chip jumpers
  RAM Chip Voltage K2 K3 K4 K5 K6
  CY62167E 5V 2-3 2-3 1-2 2-3 2-3
  CY6216DV30 3.3V 1-2 2-3 1-2 2-3 2-3
  AS6C3216 3.3V 1-2 2-3 1-2 2-3 2-3
  AS6C6416 3.3V* 1-2 1-2 1-2 2-3 1-2
Be absolutely sure you have the RAM chip voltage set correctly with jumper K2.
If in fact you never intend to change the RAM chip type you might consider soldering in a small wire jumper in
Below is the jumper arrangement for the typical V06c mezzanine RAM boards we have used in the past.
   8X2MG Mezzanine Boards
The Z80 memory map should again show all "R's" in the S100 bus 64K address space except for the monitor ROM.
A good test is to insert  the IDE/CF card board in the bus and boot
Another test is to insert an 8086, 80286 or 80486 CPU slave board and do a Memory Map with those CPU's or boot MSDOS.

Note the "old" V06c RAM mezzanine mini-boards will not take the new 8MG X 8  (
AS6C6416) RAM chips. There is no input pin for the extra A23 address line. 
If you solder the two 8MBX8 SMD chips to the board this is clearly a problem.
I have updated the RAM mezzanine board with a jumper to allow one
AS6C4164 chip to be used (instead of two 4MBX8 or four 2MBX8 chips). 
I call this mezzanine mini-board  "V7.0".
    8MB Mezzanine board
For the 8MX8 RAM chips the A23 jumper must be added as well as the jumper
JP5 on the board itself
For all other RAM chips the A23 jumper should not be used nor should
JP5 on the S100 board itself be installed.
Since most people probably have the V06c boards I will not do a run of the V7.0 boards unless there is a demand.  The KiCad/Gerber files for the V7.0 mini-boards is included below.

One surprise I found with the AS6C4164 chips / V7.0 Mezzanine RAM boards, they seem to actually work better with high speed 80486's etc. using 5V instead of 3.4V. 
The Alliance Memory Spec sheet for these chips has a Max of 4.6V, so do so at your own risk particularly if you use another manufacturer's chip.  At least in my case they run for days at 5V.

Here is a picture of the V7.0 mezzanine setup.
    2MG X 8 Mezzanine

Two 8MB X8 48 pin TSOP SMD AS6C6416 chips soldered directly to the board.
This is clearly the most efficient way to add 16MG of RAM to the board.  If you feel comfortable soldering the two RAM chips to the board do it this way.
I have on purpose added extra long SMD solder pads to the board.  Everybody seems to have their own way to do the soldering.
I find the easiest and most reliable is to:-
1.    With a brush add a layer of flux paste to the RAM pin pads. Just enough to wet the pads.
2.    Melt a little drop of solder to the iron tip and spread the melt along all the pins.
3.   Check there are no pad cross bridges. If the are swipe the solder tip along the pins
4.   Place the RAM chip on the pads and align its pin 1 to the top left corner of the pads. Use a blade and twist it to align pin 1 to its pad, Be sure its midway along the pad
5.   Briefly touch just the RAM chip Pin 1 with the iron tip while pressing down on the chip with your finger. The RAM pin will fuse with the solder on the board.  Only pin 1.
6.   Go to pin 25 and carefully align it with its pad, again using a blade to move the chip.  Do a spot check to be sure all pads are aligned correctly.
7.   Again briefly touch just the RAM chip Pin 25 with the iron tip while pressing down on the chip with your finger. The RAM pin will fuse with the solder on the board.
8.   Run a very thin layer of solder flux along the RAM pins.
9.   Then go around the chip briefly touching each pin separately. The slightest touch is all that is required.
10. Then with your blade place it between each RAM pin and check it does not move.
11.  Finally wash the chip area with flux remover and blow dry.

Here is a picture of two AS6C6416 chips soldered directly to the board.
    2X8 SMD RAM

The Board LED's
The Board has a number of diagnostic LED's along the top left hand side. This is useful for debugging. They are shown below.
   Board LED's
Whenever there is any access to the board by the current bus CPU master the "Blue" LED lights up.  
The 4 "Red" LED flash whenever the current bus CPU issues am 8 bit RAM read, write or a 16 bit RAM read or write. 
Because these signals are too narrow to see LED flashes the flashes themselves are stretched using the 74LS123's U7 and U16.
Any ROM 8 or 16 bit Read will also cause the corresponding LED to flash.

If wait states are added to the ROM reads the "Yellow" ROM wait LED will light up.
If the actual ROM is active the "Green' LED will stay lit.

16MG RAM Only
Peter Higgins assembled a minimalist "16MB RAM only" build of the RAM+ROM II board.
The only modification was to supply the input of the LM3940 from the output of the 5V regulator and to cut the existing trace leading to the 8V bus supply.
Here is a picture of his setup.
   16MG RAM Only

He has also supplied a BOM for the board in that configuration here.

Rich Camarda has the board wunning with the pre-IEEE-696 Croemmco ZPU (the ZPU needs the A16-A23 lines grounded, see the header he added in photo).
    Non IEEE Board

None noted so far! 
However please keep in mind this is a IEEE-696 compatible RAM board.  The original Altair and IMSAI implemented a subset of these specs. Some rework is necessary to use this RAM board with these vintage computers. For example this RAM board implements address lines A16-A23, the PHANTOM line, and the sxTRQ line - which are not implemented on the Altair and IMSAI. You should not leave these lines floating if the board is used in an Altair or IMSAI, which requires addition of jumper wires to the RAM board to ground A16-A23 and pull ups be provided to substitute for the absent of PHANTOM and sxTRQ signals. (Our SMB V3 has jumpers to address this issue).  It should work with all S100Computers,  Compupro,  Intersystems, SD Systems etc. boards.

Source of Chips
Most of the chips on this board are quite common.  A good source of 74LSxx and 74Fxx chips is Jameco, Mouser or DigiKey.
The 512K Static RAMs can be obtained from Jameco,  #1927617.  28C64A's the same, #74827.
The SMD RAM chips are from DigiKey. The 8GB X 8 (AS6C4164 chips) are Part Number is 1450-1464-ND
To Order a Production S-100 Board
A number of people may want to utilize a board like this.  Together with a group of people on the  Google Groups S100Computers Forum. a group order was done.
The "group purchases" is now closed.

 (V1.4    1/24/2023)
        (V1.4  1/24/2023)
Most current Gerber files for this board   (.zip file)                       (V1.4  1/24/2023)
Most current KiCAD files for this board    (.zip file)                       (V1.4  1/24/2023)
KiCad/Gerber files for the V7.0  Mezzanine Board  (.zip file)        (V1.0 1/2/2023)
BOM List of components (.Pdf File)                                    
(V1.0 3/31/2023) (Supplied by Rick Bromagem)
BOM List of components (.XLS File)                                              (V1.0 3/31/2023) (Supplied by Rick Bromagem)

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This page was last modified on 07/22/2023